* Microcode Assembler 1.0 NOV 2019 * * TTL CPU CORE STYLE MEMORY 20 bit CPU 74LS181 74LS170 74LS195 TRSTATE BUFFERS 2 256 x 8 ROM 65 NS MAJOR STATE 1 256 x 8 ROM 65 NS ALU DECODE VERSION #1 .7 us (14.32 MHZ/2) / 5 NOV 18 2019 TTL DECODE _##___##__ CLK __##___##_ ACLK ##___##___ ECLK _#####____ MREQ (READ) #_____#### WRITE/WRITE BACK <---><###> DATA OUT ----><---- R/W SWR 72 PIN CARD EDGE CONNECTOR 1,2 GND 3 VCC 4..24 MAR/OUT BUS IN 25 ~CLK ~CLKE WA1 WA2 26 ~CLKA RESET CYI ~CYO 27 FETCH ~IRQ SH1 SH0 28 BY SWR SHI WRAM 29 MREQ WR RA1 RA2 30 BRUN (res) S0 S1 31 (-12?) S2 S3 32 (+12?) SGN ODD 33 (CORE?) K1 K2 34 PAN1 PAN2 K3 K4 35 PAN3 DSP K5 K6 36 SW1 SW2 M SH[1..0] 74194 00 - 01 LEFT 10 RIGHT 11 LOAD K1 KONSTANT K2 WORD DATA K3 SEX K4 0/2 K5 LOAD INPUT K6 ADX '/' LINE COMMENT '*' BLOCK COMMENT LINE BEGINING/END ONLY #OOO OCTAL PROGRAM COUNTER LINE TOKENS PROM A PRA# ctl 0001 0 wrd 0002 1 sx 0004 2 2 0008 3 op 0010 4 ld 0020 5 ~no 0040 6 sft 0080 7 PROM B PRB# by 0100 0 ir 0200 1 rd 0400 2 (mreq) wr 1000 4 pc 0000 ac 0800 3 ix 2000 5 stk 4000 swr 8000 7 dsp ix+ac 20 bits / 10 bit bytes +--------------------------+ |oX:ooo:aaB:xx+:###:###:###| -+ 512 mem +--------------------------+ +--------------------------+ |11:1o1:aaB:xx+:###:###:###| -+ 512 store +--------------------------+ +--------------------------+ |1X:101:000:xx+:###:###:###| JSR +--------------------------+ +--------------------------+ |1X:101:001:xx+:###:###:###| JMP +--------------------------+ +--------------------------+ |00:ccc:00i:+##:###:###:###| BCC n*2 +--------------------------+ +--------------------------+ |00:101:000:000:000:000:000| HLT +--------------------------+ +--------------------------+ |00:111:001:0E0:000:000:000| EI/DI +--------------------------+ +--------------------------+ |01:ccc:00i:+##:###:###:###| SCC +--------------------------+ +--------------------------+ |10:101:aa0:xx+:###:###:###| LEA +--------------------------+ +--------------------------+ |10:1L1:aa1:SC : : ##:###| SHIFT -1 to -20 +--------------------------+ X 0 # 1 INDEXED op 0/4 aa xx ccc 0 sub/imp jmp z False 1 add/eqv a a Z 2 sbc/ld x x S 3 adc/and s s S+Z 4* ---/--- C 5 adx/st - 6 xor/or True 7 bit/st - * reserved NORMAL <0:? ><1!m!m> PANEL * / PANEL #040 / idle pc pc pc dsp no pc pc ir #050 / aload pc rd swr pc swr pc ld wrd pc 2 op /sub pc pc ir #060 / examine pc 2 rd pc pc ac ld wrd pc pc ir #070 / deposit pc rd swr pc swr pc 2 rd wr ac ld wrd wr pc pc ir / PANEL STORE is DON't CARE #140 / idle pc pc pc dsp no pc pc ir #150 / aload pc rd swr pc swr pc ld wrd pc 2 op /sub pc pc ir #160 / examine pc 2 rd pc pc ac ld wrd pc pc ir #170 / deposit pc rd swr pc swr pc 2 rd wr ac ld wrd wr pc pc ir / MEMORY #210 / word direct ix sx no rd ac pc 2 rd ac op wrd ir #200 / word # pc 2 rd ac pc 2 rd ac op wrd ir #230 / byte direct ix sx no rd by ac by pc 2 rd ac op sx ir #220 / byte # pc 2 rd ac op sx ir pc 2 rd / don't care ac ir #240 / bcc - trap - hlt ac no op ld pc 2 rd dsp ctl no ir pc / trap pc ld no rd wr pc wr pc 2 ld rd pc ir #250 / scc ac no op ld ac ld pc 2 rd dsp no ir #260 / bcc - ei/di ac no op ld pc 2 rd dsp ctl no ir #270 / scc ac no op ld ac ld pc 2 rd dsp no ir / STORE #310 / word direct ix sx no rd wr ac wr pc 2 rd dsp no ir #300 / lea pc 2 rd ix sx ir rd #330 / byte direct ix sx no rd by wr ac by wr pc 2 rd dsp no ir #320 / shift ac no ac sft / hold count? pc 2 rd dsp no ir #350 / jsv word direct ix sx no rd pc 2 stk rd wr pc wr pc ld wrd rd pc ir #340 / jsv # pc 2 rd pc 2 stk rd wr pc wr pc ld wrd rd pc ir #370 / jmp word direct ix sx no rd pc pc ld wrd rd pc ir #360 / jmp word # pc 2 rd pc pc ld wrd rd pc ir * ROMA - ROM A PAL/OR PROM 256x8 ROMB - ROM B PAL/OR PROM 256x8 ROMTC - ALU DECODE 00 3A 01 3A 02 3A 03 3A 04 3A 05 3A 06 3A 07 3A 08 26 09 26 0A 26 0B 26 0C 26 0D 26 0E 26 0F 26 10 29 11 29 12 29 13 29 14 29 15 29 16 29 17 29 18 46 19 69 1A 46 1B 69 1C 46 1D A9 1E 16 1F 17 20 3A 21 3A 22 3A 23 3A 24 3A 25 3A 26 3A 27 3A 28 26 29 26 2A 26 2B 26 2C 26 2D 26 2E 26 2F 26 * $