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 Programmable logic 
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No unread posts   Attachment(s) Help/Critique for a design with an ATF1508 CPLD

DoctorWkt

5

14446

Thu Aug 31, 2023 10:40 pm

DoctorWkt View the latest post

No unread posts   Floating Point Library

robfinch

0

17771

Tue Feb 22, 2022 3:12 am

robfinch View the latest post

No unread posts   Attachment(s) Noc - Network on chip

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robfinch

24

31099

Mon Jan 03, 2022 9:13 am

robfinch View the latest post

No unread posts   Making wide(r) memory from byte-wide memory?

tingo

4

4661

Mon Dec 14, 2020 8:50 am

tingo View the latest post

No unread posts   Resources for Newbie Verilog and VHDL People

DoctorWkt

13

17598

Tue Jun 16, 2020 9:33 pm

quadrant View the latest post

No unread posts   Attachment(s) clock division w/ CPLD

shoggoth

3

7587

Fri May 08, 2020 6:08 am

BigEd View the latest post

No unread posts   programmer mode bug in quartus 9.0 (altera)

oldben

3

5045

Thu Dec 26, 2019 10:46 pm

oldben View the latest post

No unread posts   How do I determine when SRAM is ready from a CPLD?

cbmeeks

4

7213

Sun Aug 04, 2019 5:05 am

barrym95838 View the latest post

No unread posts   Verilog code review for 8-bit computer

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fmahnke

18

20475

Wed Feb 20, 2019 9:25 am

BigEd View the latest post

No unread posts   Attachment(s) TOYF (Toy Forth) processor

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Hugh Aguilar

78

64308

Fri Nov 09, 2018 8:14 pm

Hugh Aguilar View the latest post

No unread posts   j68 - a 68000 implemented on a forth microarchitecture

BigEd

9

23983

Fri Mar 02, 2018 6:39 pm

NorthWay View the latest post

No unread posts   LiteX - an open source FPGA front end

BigEd

0

7229

Mon Oct 30, 2017 11:47 am

BigEd View the latest post

No unread posts   Attachment(s) 65ISR

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Hugh Aguilar

35

36574

Thu Oct 12, 2017 4:10 am

Hugh Aguilar View the latest post

No unread posts   Seeking the smallest 68000 implementation...

BigEd

8

16354

Tue Sep 19, 2017 5:45 pm

BigEd View the latest post

No unread posts   The ZIP cpu - a pipelined RISC

BigEd

0

7055

Mon Sep 11, 2017 2:28 pm

BigEd View the latest post

No unread posts Attachment(s) Ben Eater's SAP inspired computer implemented in VHDL

Xark

3

8871

Fri Aug 25, 2017 3:03 pm

BigEd View the latest post

No unread posts   Attachment(s) xr16 - a tiny RISC, with CPU design tutorial and SoC design

BigEd

0

6873

Mon Jul 24, 2017 12:16 pm

BigEd View the latest post

No unread posts   Tactics for small and fast FPGA implementations

BigEd

2

7138

Fri Jul 14, 2017 5:11 pm

BigEd View the latest post

No unread posts   Attachment(s) Parallella, $99 "Linux Supercomputer" (with FPGA)

BigEd

7

16182

Thu Dec 22, 2016 9:19 am

BigEd View the latest post

No unread posts   Attachment(s) A Forth CPU on FPGA for homebrew GPS

BigEd

2

8698

Wed Nov 09, 2016 4:58 pm

BigEd View the latest post

No unread posts   Multi-port Memory Controller

robfinch

4

9669

Thu Apr 28, 2016 4:22 am

robfinch View the latest post

No unread posts   Small FPGA CPU

Arlet

11

15758

Wed Dec 09, 2015 4:42 am

Arlet View the latest post

No unread posts   Clock Wars

robfinch

5

11180

Fri Feb 06, 2015 9:41 am

robfinch View the latest post

No unread posts   Propeller 2 on FPGA

BigEd

0

6841

Sun May 25, 2014 10:59 am

BigEd View the latest post

No unread posts   SPARCStation on FPGA

BigEd

0

6867

Tue May 20, 2014 7:47 pm

BigEd View the latest post

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