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Simulating the Gigatron TTL Computer in a Logic Simulator.
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Author:  monsonite [ Wed Aug 04, 2021 2:16 pm ]
Post subject:  Simulating the Gigatron TTL Computer in a Logic Simulator.
The Gigatron TTL Computer is an 8-bit Harvard architecture cpu built from about 40 TTL ICs plus a modern 64K x 16-bit ROM and a 32K x 8 RAM.

I have owned a Gigatron for a few years, but only just got around to transcribing it's schematic into a Logic Simulator.

I have placed a copy of my Gigatron simulation on my Github repository. It is a close copy of Marcel van Kervink's original design, but substitutes some components, for some more "bus friendly" devices.

https://github.com/monsonite/Gigatron-Simulator

I use H. Neemann's "Digital" simulator - which is a follow-on from the original "Logisim" that is no longer supported.

You can download "Digital" from H. Neemann's Github repository:

https://github.com/hneemann/Digital

I have created a comprehensive "Front Panel" which allows the user to monitor the various address and data buses, the principal registers and the various control signals.

Whilst the original Gigatron was designed to produce colour VGA graphics and sound - this simulation is intended as a simplified version, to explore the architecture and instruction set.
Author:  BigEd [ Wed Aug 04, 2021 3:52 pm ]
Post subject:  Re: Simulating the Gigatron TTL Computer in a Logic Simulato
Very nice... but I think we should include your picture:
Image
Author:  Ken KD5ZXG [ Sun Sep 04, 2022 12:37 am ]
Post subject:  Re: Simulating the Gigatron TTL Computer in a Logic Simulato
By coincidence, I offer a ripple-free way to compare EQ,LT,GT per Gigatron's jump mode bits.
Also simulated in "Digital" because it handles pass-through logic.
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