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 j68 - a 68000 implemented on a forth microarchitecture 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 579
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Frederic Requin wrote an open source 68000 core called J68. It's microcoded but with a two-stack forth-like approach, and comes out pretty small. Only caveat is that there's 3x clock cycle penalty, so a 50MHz implementation would match a 16MHz 68k.

(There's another version here which I think might be a little older.)

The comments describe it like this:
Quote:
// Simple re-implementation of the MC68000 CPU
// The core has the following characteristics:
// - Tested on a Cyclone III (90 MHz) and a Stratix II (180 MHz)
// - from 1500 (~70 MHz) to 1900 LEs (~90 MHz)
// - 2048 x 20-bit microcode ROM
// - 256 x 28-bit decode ROM
// - 2 x block RAM for the data and instruction stacks
// - stack based CPU with forth-like microcode
// - not cycle-exact : needs a frequency ~3 x higher
// - all 68000 instructions are implemented
// - all 68000 exceptions are implemented


Found via a comment to Experimenting with TG68:
Quote:
The big advantage of the J68 is its size : 2000 LEs instead of 3500-4000 LEs.
I do know that by doing the instruction fetch/decode in parallel with the execute, the performance will be almost doubled.
For the moment, I have been too lazy to do it :-).

... and indeed that whole blog series about the TG68-based miniSOC is worth a look. Index here:
http://retroramblings.net/?page_id=770
Quote:
Part 1 – A Counter
Part 2 – A VGA Controller
Part 3 – Writing to the Framebuffer
Part 4 – Improving memory performance
Part 5 – Interrupts and other tweaks
Part 6 – A Sprite and a Simple UART
Part 7 – The Mouse
Part 8 – Timers and C Code
Part 9 – Accessing the SD Card
Part 10 – Multiple Boards
Part 11 – Porting to the Turbo Chameleon 64
Part 12a – A Better Cache
Part 12b – A Better Cache
Part 13 – Timing Closure at Last
Part 14 – Improving the SDRAM controller


Mon Jan 09, 2017 12:12 pm
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