xr16 - a tiny RISC, with CPU design tutorial and SoC design
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Author:  BigEd [ Mon Jul 24, 2017 12:16 pm ]
Post subject:  xr16 - a tiny RISC, with CPU design tutorial and SoC design

(Via hoglet and also via Rob Finch, whose Butterfly CPU is influenced by xr16)

xr16 is a late-20th century 16 bit RISC homebrew, for education purposes, by Jan Gray, with a number of notable features:
- only 91 slices
- described in a short series of articles which explain design process and design decisions
- with a C compiler which came before the instruction encoding which came before the implementation
- three-operand instructions, 16 element register file
- pipelined
- bigendian
- supports one level of interrupts
- uses a prefix instruction to allow loading of full 16 bit values, uninterruptable
- has no carry bit or processor flags
- supports multi-word arithmetic by making add, sub and compare uninterruptable
- carefully floorplanned in FPGA
- comes with an SoC design called XSOC

xr16-floorplan.png [ 66.33 KiB | Viewed 2719 times ]

The short series of articles is in this PDF

There's a PDF presentation on the machine and the process here.

There's a copy of the source here on github for easy browsing.

Note the license: it's not open source, but is revocable and for non-commercial use only.

Since the xr16, Jan has gone on to make a series of CPUs, including massive arrays of network-on-chip CPUs. Worth looking around his site.

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