|The ZIP cpu - a pipelined RISC
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|Author:||BigEd [ Mon Sep 11, 2017 2:28 pm ]|
|Post subject:||The ZIP cpu - a pipelined RISC|
Just found this blog, with much about CPUs on FPGAs, including a CPU - the ZIP CPU.
"A small, light weight, RISC CPU soft core" with five pipeline stages.
by Dan Gisselquist
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