LiteX - an open source FPGA front end
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Author:  BigEd [ Mon Oct 30, 2017 11:47 am ]
Post subject:  LiteX - an open source FPGA front end

This quote explains it all, I think:
LiteX produces a design that uses about 20% of an XC7A50 FPGA with a runtime of about 10 minutes, whereas Vivado produces a design that consumes 85% of the same FPGA with a runtime of about 30-45 minutes.

LiteX is a soft-fork of Migen/MiSoC – a python-based framework for managing hardware IP and auto-generating HDL. The IP blocks within LiteX are completely open source, and so can be targeted across multiple FPGA architectures. However, for low-level synthesis, place & route, and bitstream generation, it still relies upon proprietary chip-specific vendor tools, such as Vivado when targeting Artix FPGAs. It’s a little bit like an open source C compiler that spits out assembly, so it still requires vendor-specific assemblers, linkers, and binutils.

The blog post suggests that an FPGA vendor's own tools don't have a great incentive to fit your design into the smallest cheapest part.

It looks from the repo as if the frontend supports Xilinx, Altera and Lattice (the open source IceStorm backend is used for Lattice.)

I dug around in the MiSoC libraries a bit and there seem to be some serious logic designs using this Python syntax. I’m not sure I want to wrap my head around this coding style, but the good news is I can still write my leaf cells in Verilog and call them from the high-level Python integration framework.

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