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| LiteX - an open source FPGA front end http://anycpu.org/forum/viewtopic.php?f=13&t=479 |
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| Author: | BigEd [ Mon Oct 30, 2017 11:47 am ] |
| Post subject: | LiteX - an open source FPGA front end |
This quote explains it all, I think: Quote: LiteX produces a design that uses about 20% of an XC7A50 FPGA with a runtime of about 10 minutes, whereas Vivado produces a design that consumes 85% of the same FPGA with a runtime of about 30-45 minutes. LiteX is a soft-fork of Migen/MiSoC – a python-based framework for managing hardware IP and auto-generating HDL. The IP blocks within LiteX are completely open source, and so can be targeted across multiple FPGA architectures. However, for low-level synthesis, place & route, and bitstream generation, it still relies upon proprietary chip-specific vendor tools, such as Vivado when targeting Artix FPGAs. It’s a little bit like an open source C compiler that spits out assembly, so it still requires vendor-specific assemblers, linkers, and binutils. The blog post suggests that an FPGA vendor's own tools don't have a great incentive to fit your design into the smallest cheapest part. It looks from the repo as if the frontend supports Xilinx, Altera and Lattice (the open source IceStorm backend is used for Lattice.) Quote: I dug around in the MiSoC libraries a bit and there seem to be some serious logic designs using this Python syntax. I’m not sure I want to wrap my head around this coding style, but the good news is I can still write my leaf cells in Verilog and call them from the high-level Python integration framework. |
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| Author: | enso1 [ Sun Feb 09, 2025 10:06 pm ] |
| Post subject: | Re: LiteX - an open source FPGA front end |
It seems that Tang Nano 20k has a litex as one of the examples. Still trying to figure out what it is as there is no source! |
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| Author: | BigEd [ Sun Feb 09, 2025 10:27 pm ] |
| Post subject: | Re: LiteX - an open source FPGA front end |
Have a look around here: (the litex bitstream, with instructions for rebuilding, is in sipeed's nano 20k repo) https://github.com/sipeed/TangNano-20K- ... main/litex |
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| Author: | enso1 [ Tue Feb 11, 2025 9:55 pm ] |
| Post subject: | Re: LiteX - an open source FPGA front end |
God damn them, it's nothing but marketing bull****. I've been digging through the wiki, but cannot figure out what it actually is. I've learned that it helps me integrate, create, and slaughter my competition (if I had any), but I still don't know what it is. I actually installed it and it pulled in hundreds of megabytes of something (against better judgment -- every time I've ever gotten into a python morass this size I've regretted it). I will keep trying, I suppose, until I am totally sick of this blatant nonsense. 5 minutes later: that is enough for me. My eyes are peeling -- I saw the worst implementation of a UART (in Verilog) as part of migen tutorial, and the last thing I want is to build circuits in Python. Now I have to figure out how to uninstall this pile of garbage. |
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| Author: | BigEd [ Wed Feb 12, 2025 6:51 pm ] |
| Post subject: | Re: LiteX - an open source FPGA front end |
Sounds like a thumbs-down from you! The tang nano 20k boards come with a litex demo, it seems like a mini-linux, running on a RISC-V, with a very simple command line as installed. But indications are that one could have a larger userspace. This is what is looks like when it boots (viewed over serial) Code: __ _ __ _ __ / / (_) /____ | |/_/ / /__/ / __/ -_)> < /____/_/\__/\__/_/|_| Build your hardware, easily! (c) Copyright 2012-2023 Enjoy-Digital (c) Copyright 2007-2015 M-Labs BIOS built on Mar 13 2023 17:09:37 BIOS CRC passed (f2b1f4f6) LiteX git sha1: b05c3069 --=============== SoC ==================-- CPU: VexRiscv_Min @ 48MHz BUS: WISHBONE 32-bit @ 4GiB CSR: 32-bit data ROM: 128.0KiB SRAM: 8.0KiB L2: 128B SDRAM: 8.0MiB 32-bit @ 48MT/s (CL-2 CWL-2) MAIN-RAM: 8.0MiB --========== Initialization ============-- Initializing SDRAM @0x40000000... Switching SDRAM to software control. Switching SDRAM to hardware control. Memtest at 0x40000000 (2.0MiB)... Write: 0x40000000-0x40200000 2.0MiB Read: 0x40000000-0x40200000 2.0MiB Memtest OK Memspeed at 0x40000000 (Sequential, 2.0MiB)... Write speed: 12.9MiB/s Read speed: 16.1MiB/s --============== Boot ==================-- Booting from serial... Press Q or ESC to abort boot completely. sL5DdSMmkekro Timeout No boot medium found --============= Console ================-- litex> |
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