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 Oldland - a 32bit RISC, open source, cache, GNU toolchain 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1780
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Open source, and with an SoC wrapper too (called Keynsham) and also with a C model. Might even support a linux port. By Jamie Iles.

Quote:
Oldland is a 32-bit RISC CPU targeted at FPGAs. The main features are:
    5 stage load/store pipeline.
    16 general purpose registers.
    N-way set-associative blocking instruction/data caches
    Software managed instruction/data TLBs with 4KB page size.
    JTAG debug controller for execution control and state modification/inspection.
    Exception table for interrupts, data/instruction aborts, illegal instruction and software interrupts along with separate ITLB/DTLB miss handlers.
    User and supervisor modes
- from http://jamieiles.github.io/oldland-cpu/

Runs at 75MHz. Interesting to have something with a cache and SDRAM support.

Image

Quote:
There are three different simulators for the CPU:
    oldland-sim: an instruction set simulator in C and is not cycle accurate.
    oldland-rtlsim: an Icarus verilog simulation, models events but can be slow.
    oldland-verilatorsim: a Verilator based simulation that runs > 1MHz and is cycle accurate.
The Icarus simulation is the most accurate and includes vendor models of the SDRAM whereas the verilator model does not model SDRAM timing or configuration.


via http://hackaday.com/2015/03/20/the-oldl ... fpga-core/


Sat Jan 14, 2017 1:49 pm
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Joined: Thu Jan 17, 2013 4:38 pm
Posts: 53
Finally someone did separate TLBs! Or am I missing out on some other designs that have already done so?


Sat Jan 14, 2017 8:06 pm
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