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 Suite-16 (formerly Bitslice using currently available TTL) 
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Joined: Mon Aug 14, 2017 8:23 am
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After a week away relaxing on a narrowboat, mulling some thoughts, I am now re-engaged in my TTL computer design.

I have settled on a name for the project "Suite-16" that pays homage to Steve Wozniak's Sweet-16 interpreter and also reflects that this is a 16-bit processor.

The aim of the project is to design a 16-bit ISA that can be simulated in software, implemented in under 80 TTL ICs or on a low cost FPGA.

My motivation is that I have just begun a sabbatical year with the aim of learning more about cpu architectures, simulation in C and verilog on FPGAs. I also want to explore the performance of different architectures - including those that use registers and those that are stack machines. Hopefully in a year's time I will have something working in real TTL, also running on an FPGA using verilog, and simulated in C.

I have also come across a new digital logic simulator called "Digital" with which I hope to simulate large sections of the design - before I start pushing 30 year old TTL ICs and wires into breadboards.

One of my influences is Brad Rodriguez's PISC (Pathetic Instruction Set Computer). https://bradrodriguez.com/papers/piscedu2.htm

Back in 1994 it was possible to build this in TTL, but now several of the key ICs have become obsolete. I am trying to find a cost-effective way of engineering around this minor inconvenience. Right now I am converting the PISC design into something that can be built as a bit-slice design using currently available TTL chips. Hopefully the end product of this will be offered as a PCB that anyone can build.

My intention is to use the ALU which Marcel uses in his Gigatron design. (Originally proposed by Dieter Muller). With four multiplexers and an adder you can replace the now obsolete 74xx181 ALU - so this will be at the heart of my bitslice design.

Whilst I would love to recreate an MSP430 from TTL - I suspect that this exceeds my capability, and by restricting the register-register operations to register-accumulator operations, you can save a whole lot of hardware in not having separate source and destination fields specified in the instruction. This nicely aligns the machine's capabilities with that of Woz's Sweet-16.

My simulations of the machine with "Digital" are progressing, and I now have a lot of the architecture defined. It's always a trade-off between the instructions that you want - and those that you can implement easily in TTL. My mantra for this project is "Don't design anything you cannot build". So I will try to keep things simple - especially with the TTL.

When Brad Rodriguez designed PISC - is was intended as an exploration of stack machine architecture. It may fail miserably as a conventional 1 or 2 operand machine, but it excels at its design mission - implementing Forth primitives at (on average) 4.5 times faster than an 8086 of equal clock frequency.

I'm hedging my bets by having an architecture that uses a register file that may also be used as a parameter stack. A 4-bit presettable up-down counter will provide a stack pointer, or you can override it and address the register file directly.

I will be putting any relevant info on my Github page https://github.com/monsonite/Suite-16

If anyone wants to discuss minimal 16-bit designs - I'd only be too happy to engage.


Last edited by monsonite on Tue Sep 24, 2019 4:31 pm, edited 1 time in total.



Tue Sep 24, 2019 3:10 pm
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Excellent! Will follow with interest. I find it particularly interesting to see trade-offs explored - not just a finished project with all decisions final, so I hope you're able and willing to post your wandering progress.


Tue Sep 24, 2019 4:22 pm
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Today I have been looking at the practical implementation of the cpu using TTL.

With a 16-bit cpu, things can very quickly get large and complex, so I thought that I'd look at the ALU first - as it is a fairly well defined unit, it represents a fair chunk of the design and easily built from TTL. However it will be a minimum of 24 ICs on a 100x100 mm circuit board. It's important that we pick a connector arrangement that can handle the various buses.

The ALU has two 16-bit inputs, and one 16-bit output. Let's call them A, B and Q for the moment. It also has a 5 bit instruction input, a Carry-In input, a Carry-Output, and a clock input. When we include power and ground, we are looking at a self contained module with a minimum of 58 connections.

If we allow for a few spare, 64 seems a good round number, and the DIN41612 range of backplane connectors are fairly cheap, provide a 2.54mm pin pitch and are available in 32, 64 and 96 ways. They are intended for a single Eurocard sized pcb - which is 100 x 160mm. With the A, B and Q buses specified, that leaves a whole 32 pin row of a DIN41612 for the address bus and other control signals

I have modeled the ALU using the "Digital" circuit simulator and all seems to work as intended. Tomorrow I will convert it into a circuit schematic, with lots of decoupling capacitors and real physical component footprints. From that I will generate a pcb layout, so I at least have a starting point for Suite-16.


Wed Sep 25, 2019 5:14 pm
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I've made some progress with the bit-slice cpu - at least in terms of simulating it using "Digital".

I now have enough experience of "Digital" to quickly change the contents of Eproms, and use the 7-segment display device so that I can see the state of the various buses.

This is now becoming just like bread-boarding, except that it's a simulation and you can quickly try out new ideas, and park those that stand no chance of flying. You can single step the clock, or apply a very low Hz continuous clock to see that things are sequencing correctly.

As a trial exercise to familiarise myself with the tools and techniques, I have decided upon a much simpler cpu design based on the 4 bit ALU and slice components. I figured that if I can get the 4-bit slice to work correctly, with the various addressing modes, then putting 4 of them together to make a 16-bit machine should be a whole lot easier.

So far the simulated hardware consists of about 20 ICs. Six of them are the ALU, then there's the PC, and instruction EPROM with instruction and data registers and an instruction decoder - very similar to the diode array used in Gigatron.

The 8-bit instruction word is divided into an upper 4 bit field for the opcode, and the lower 4 bit field for either the address of the register I want to access or a 4-bit immediate data word, which can also be used as a jump address.

An immediate is first loaded into the accumulator, where it can be placed on the bus and loaded into one of the 16 registers in the next instruction. You can then perform simple operations between the accumulator and the register and store the result back into the register.

I currently have one unconditional jump instruction which can return you to some earlier point in the loop. It may sound fairly trivial but its been a good exercise in thinking how to make hardware do real work.

Conditional branches and register indirect addressing of a yet to be added RAM chip are planned for this weekend.

Any significant progress is posted to my Github repo - along with some updated project notes.

https://github.com/monsonite/Suite-16


Fri Sep 27, 2019 4:43 pm
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Nice progress. Regarding "Digital" simulator, I have also downloaded it (yes, it seems to run fine on macs too), and by just navigating the menus and trying a couple of simple things it definitely looks as a great product, albeit possibly still slightly immature. But well, it's not even reached version 1.0 yet !. I planned to use Logisim before, but I think it will be easy and advantageous to switch to Digital now, so thanks for having pointed that. I'll keep watching this thread for updates on your design.


Wed Oct 02, 2019 6:35 am
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Hi Joan,

Good to hear that you are making progress with "Digital". It takes a little while to understand the user interface, but it's a good way to do virtual "breadboarding" - and it also gives us a format for sharing design ideas.

It also offers support for GALs and ATF150x series of CPLDs. These devices are still readily available - from Mouser and other distributors. They may offer a means of reducing the amount of board space needed needed by certain sub-systems - or replace building blocks that are very bulky if built out of standard TTL, such as register files and dual port memory. Indeed there have been challenges in the past to put a full working cpu onto a 128 macrocell CPLD.

https://www.mouser.co.uk/Search/Refine?Keyword=ATF150

Whilst one of the end results of my sabbatical will be a cpu implemented in TTL - I realise that it will only be one small part of the exercise. Part of the purpose of this project is to learn new tools and techniques - of which CPLD/FPGA will also be explored. I look at these as necessary means to get the job done, and having hands-on experience of at least one hardware design language is a good skill to have these days.

The other major part of the project will simulation of the ISA in C code. I made a start on that yesterday, and I am working in parallel on it as well as my "Digital" breadboarding. It will be a good way of testing various instructions - and as I will only have a minimal instruction set - it will be a good way of determining which instructions are essential, and those which are unlikely to be used.

To sum up my project - I am exploring the triangular space bounded by the vertices of TTL design, FPGA/HDL and Code simulation.


Wed Oct 02, 2019 11:48 am
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I use a quad paper and a pen for all my TTL design. It may be old school but I don't need to have some special program around to see a schematic. Later I will need to find a good free schematic capture and PCB lay out for my designs.
I want full featured 18 bit designs,but a 4 adresss machine with the operation
(B)=(B)-(A). if B<0 JMP(C) else jump (D) is as simple as you can get.


Mon Oct 07, 2019 7:06 am
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oldben wrote:
Later I will need to find a good free schematic capture and PCB lay out for my designs.

I have been designing circuits and laying out PCBs for 30 years in my work, and there are things about every schematic-capture software that I greatly dislike, so I still do my schematics by hand, and I don't get layout errors. My most complex board had about 500 components (and the schematic was on C-size velum, ie, 18"x24", very small, with pencil), but it was mostly analog; so it would be interesting to see how it compares. There's an example of my hand drawing at http://wilsonminesco.com/6502primer/pot ... ml#BAS_CPU . I don't do much digital for my job. Don't let anyone tell you you have to have schematic-capture software before you can lay out a PCB. (I do use CAD for the PCB layout though.)

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Mon Oct 07, 2019 7:40 am
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Looks at the page. Arggg another 6502 design, there will none left in the future for Bender's brain.
Nice schematic. Do you have any notes on going to and from 5 volt ttl logic 3.3v volt devices like a FPGA or SD sd card? I have lots of 5V PAL CMOS 22v10's so I good there. With my TTL cpu design I need 3 small proms, Two 256x8 roms for microcode tables and a 32x8 rom for 74181 decoding. 22V10's
fit the bill nicely.


Wed Oct 09, 2019 4:57 am
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monsonite wrote:
Good to hear that you are making progress with "Digital". It takes a little while to understand the user interface, but it's a good way to do virtual "breadboarding" - and it also gives us a format for sharing design ideas. .


Hi Ken,

I am now starting having mixed feelings about "Digital". I like many of the design options that are missing on Logisim, but the user interface is just not working properly for me, at least on my mac. The right mouse button is not working, you must use ctrl-shift instead like on the one-button-mouse of the original Macintosh. This issue is even documented in the manual, so the developers are aware of it. But the most annoying part is that wire connections are not preserved when components are moved around. Wires just always remain in the place I first set them regardless of components being dragged to different positions, so I need to wire them again. I wonder if this also happens to you (?). Logisim does a much better job at that (I downloaded Logisim-evolution), but then I miss some of the Digital features, such as the more extensive 74xx part library and what is found under the Analysis menu option.

John


Wed Oct 09, 2019 6:58 am
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oldben wrote:
Nice schematic. Do you have any notes on going to and from 5 volt ttl logic 3.3v volt devices like a FPGA or SD sd card?

I missed this earlier. Most of the cross-voltage interfacing I've had to do has been to 12V circuits and didn't need to be very high speed. You might look into the 74LVCxx family though (which is high speed), and there are also the 74LS06 (inverting) and 74LS07 (non-inverting) open-collector hex buffers. I recently made a programming fixture for work to program 3.3V Bluetooth modules with my 5V workbench computer, and used the 74LS07.

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Wed Oct 09, 2019 6:39 pm
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Hi Ken, I read your posts and try to figure out what you want to build. You have ideas about the 'Gigatron' ALU and the xx194 shifter in the ALU, but it seems that you did not yet set out a direction for the rest of the project. A few months ago I made a list of choices that are involved when designing a CPU, and I think the list is not at all complete. It might help you think about the direction to take. Some of the questions are already answered (you use TTL and not relays).

- Performance low/high
- Cost low/high
- Number of components low/high
- Physical size big/small
- What software should it run

Architecture
- Harvard / von Neumann
- number of registers
- general registers or dedicated registers
- number of ALU functions
- support interrupts ?
- register width
- databus width and address bus width
- hardwired or microcoded control
- width of microcode
- complexity of instructions
- addressing modes
- instruction width
- instructions fixed size or variable size
- binary or something else (ternary ? analog ?)


Technology (slowest first)
- mechanic
- relay
- neon tube
- vacuum tube
- transistor
- TTL IC
- 3.3 or 5 volt for IC's ?
- CPLD
- FPGA
- mixed
- emulate on other processor

Instruction set
- own instruction set
- similar or equal to wellknown ISA as 6502, 8080, Z80, PDP11, 68000, 6809

I/O
- which I/O devices to use


Fri Oct 11, 2019 9:44 pm
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Excellent taxonomy! Deserves a new thread, perhaps.


Sat Oct 12, 2019 6:36 am
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Hi Roelh,

Thank you for your excellent list - a good way to breakdown the main points and make decisions. I am still at the start of a very long project.

I wanted to build a flexible architecture which would allow me to explore a register based architecture with that of a stack machine.

The register file I have selected can easily be addressed using an up-down counter - so that 16 cell deep, stack structures can be implemented.

The ALU will be common to both architectures.

Instructions implemented in the ALU are ADD, SUB, AND, OR, XOR, INV, SHL, SHR

The speed will ultimately be dictated by the worst case carry propagation time to perform a 16-bit ADD with carry.

My influences include Charles Moore's MISC architectures from the mid-1980s including the Novix, James Bowman's J1 Forth CPU, Brad Rodriguez's PISC and Myron Plichota's Steamer-16.


- Performance low/high 12.5MHz clock - to give compatibility with VGA, and based on the success of overclocking the Gigatron at 12.5MHz.

- Cost low/high - Low cost using off the shelf DIL packaged TTL parts and low cost 4 layer pcbs from China.

- Number of components low/high Between 80 and 100 ICs. Built as 4 identical 4-bit slices containing perhaps 16 ICs each

- Physical size big/small Approximately 20 x 30 cm - arranged over 2 or 3 pcbs

- What software should it run - Forth, BASIC and possible emulation of classic microprocessors

- Architecture- Von Neumann (Unified program and data memory)

- number of registers 16

- general registers or dedicated registers 12 general, plus PC, SP, Acc,

- number of ALU functions - 8
- support interrupts ? - maybe
- register width - 16 bits
- databus width and address bus width - 16 bit databus, 16 bit address bus
- hardwired or microcoded control - hardwired
- width of microcode N/A
- complexity of instructions - 2 operand - Accumulator plus Register (or TOS plus NOS)
- addressing modes - Register direct, Register Indirect, Immediate
- instruction width 16 bits
- instructions fixed size or variable size - fixed
- binary or something else (ternary ? analog ?) Binary

Technology - TTL IC running at 5V

Instruction set - own instruction set - with influences from Gigatron and Sweet-16 bytecode

I/O - which I/O devices to use - UART or other serial connection to terminal


Sat Oct 12, 2019 11:22 am
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Just a couple of thoughts...
- In Technology Choice, through-hole or surface mount is important, perhaps, as is presence or absence of programmable logic (GALs, CPLDs). Maybe whether battery, solar, or mains powered.
- In the OPC adventure, we found we had good productivity writing emulators in Python, and then at a later point, IIRC, we found it relatively easy (partly because of a suitably simple coding style) to rewrite the python in C.
- The question of what will run on the machine is crucial, because that software will have to be written! So there's a question of whether you intend to run a cross-compiler such as LLVM, or write in assembly code, or some other tactic. Some CPU designs will be more amenable to some choices here.


Sat Oct 12, 2019 7:28 pm
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