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Two Forth(ish) CPUs on FPGA http://anycpu.org/forum/viewtopic.php?f=15&t=126 |
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Author: | BigEd [ Tue Apr 22, 2014 9:03 pm ] |
Post subject: | Two Forth(ish) CPUs on FPGA |
We don't yet seem to have had a mention of these two: - The J1 Forth CPU by James Bowman, which powers the gameduino. Just 200 lines of verilog. http://www.excamera.com/sphinx/fpga-j1.html links to a PDF. - The Kestrel-2 CPU and SBC by Samuel Falvo - a stack-based Minimal Instruction Set CPU with an as yet unconsolidated web presence. Try these: http://www.forth.org/svfig/kk/11-2013-Falvo.txt https://bitbucket.org/kc5tja/kestrel https://github.com/sam-falvo/kestrel/tr ... S16X4A/doc http://sam-falvo.github.io/kestrel/ I see more Forth cores are listed and linked at http://www.forth.org/cores.html |
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