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YAFC - Yet Another Forth Core (VHDL) http://anycpu.org/forum/viewtopic.php?f=15&t=154 |
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Author: | BigEd [ Thu Aug 14, 2014 9:22 am ] |
Post subject: | YAFC - Yet Another Forth Core (VHDL) |
Just found this, a recent Forth core by Tim Wawrzynczak: https://github.com/inforichland/yafc which cites as influences J1 F16 C18 Quote: Specs 100 MHz 16-bit dual stack processor. Supports a generous subset of Forth primitives. 32-word deep data stack, 32-word deep return stack Supports single-cycle execution of nearly all opcodes (exceptions are jumps, branches, calling a word, or returning from a word). The overhead of calling a word (subroutine) is only 2 extra cycles, and with a 32 word deep return stack, highly factored code is encouraged. Serial (RS-232) bootloader, is the default program loaded into the onboard SRAM. There is an accompanying Python script which can send an Xilinx-style memory initialization file over your computer's UART to the running YAFC core, and then it will run that program until it is reset or turned off (several examples included). An assembler, written in Python. Note that programs are written as Python programs, and should be bootloaded into the core, after assembly. Also note that this file is a giant hack; in my defense, it was just something to get me going ASAP when I was ready to run programs in the core. 8K of Program / Memory space, and 8K of I/O space. UART and GPIO are the only (admittedly very simple) peripherals implemented as of yet. |
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