View unanswered posts | View active topics It is currently Fri Mar 29, 2024 12:00 pm



Reply to topic  [ 1 post ] 
 68000 bus timing - explained and explored 
Author Message

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1780
Steve Chamberlin has written about the 68000 bus:
Quote:
68000 Interleaved Memory Controller Design
Continuing my efforts on the Plus Too Macintosh Plus clone, I’ve started work on the design of the interleaved memory controller. The memory controller allows RAM to be transparently shared between the 68000 CPU and the video circuitry. The general principle of operation is clear, and is described in many articles about the Mac 128K/512K/Plus, as well as discussions of machines like the Amiga and Atari ST that used a similar scheme. The memory controller forces the CPU and video circuitry to take turns accessing the RAM’s address and data busses. The video circuitry is designed to guarantee that it only accesses RAM during its turn. If the CPU attempts to access RAM out of turn, the memory controller forces it to wait.

http://www.bigmessowires.com/2011/08/25 ... er-design/

Image

via hackaday


Thu Aug 21, 2014 3:01 pm
Profile
Display posts from previous:  Sort by  
Reply to topic   [ 1 post ] 

Who is online

Users browsing this forum: No registered users and 2 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Search for:
Jump to:  
cron
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software