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 RISC-V and the Sodor Processor Collection 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1372
The people at are designing an open source System on Chip using a RISC-V CPU - which is of course also an open-source design. The Sodor collection is a set of implementations of the RISC-V architecture:

This repo has been put together to demonstrate a number of simple RISC-V integer pipelines written in Chisel:
1-stage (essentially an ISA simulator)
2-stage (demonstrates pipelining in Chisel)
3-stage (uses sequential memory)
5-stage (can toggle between fully bypassed or fully interlocked)
"bus"-based micro-coded implementation


Tue Sep 02, 2014 11:44 am
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