The people at http://www.lowrisc.org/ are designing an open source System on Chip using a RISC-V CPU - which is of course also an open-source design. The Sodor collection is a set of implementations of the RISC-V architecture:
Quote:
This repo has been put together to demonstrate a number of simple RISC-V integer pipelines written in Chisel:
1-stage (essentially an ISA simulator)
2-stage (demonstrates pipelining in Chisel)
3-stage (uses sequential memory)
5-stage (can toggle between fully bypassed or fully interlocked)
"bus"-based micro-coded implementation
1-stage (essentially an ISA simulator)
2-stage (demonstrates pipelining in Chisel)
3-stage (uses sequential memory)
5-stage (can toggle between fully bypassed or fully interlocked)
"bus"-based micro-coded implementation
