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 Nat Semi's 32000 cpu family - for FPGA 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1780
National Semiconductor introduced their 32bit CISC family in 1982 - originally called 16000 and later renamed as 32000, with intended family members named according to external bus size. The 32016 had a 16bit wide memory bus.

There's lots of information about the CPU, the history, machines which used it, and a high performance HDL reimplementation for FPGA designs, by Udo Möller:
- The coprocessor for BBC micro by Acorn
- The Ceres machines by Wirth
- The M32632 HDL core by Udo
- The Titan machines by Udo


See also Wikipedia of course.

From the OpenCores page:
Quote:
The M32632 has the following features:
simple instructions are executed in one clock cycle,
8 kByte instruction cache,
8 kByte write-through data cache,
one direct mapped TLB of 256 entries for each cache,
basic floating-point instructions for 32-bit and 64-bit data types,
coprocessor interface for custom instructions,
small size of 15400 LEs,
35 MHz clock speed in Altera Cyclone IV FPGA.


Looks like the M32632 fits on a DE0-Nano board, or presumably on a cheap lookalike.
Image


Wed Jan 13, 2016 5:58 pm
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1780
Quick update on Udo's NS32k core: Dave Banks has subsetted it to fit into a much smaller LX9 FPGA - this version lacks MMU, FPU and caches, but still runs at 30MHz or so.
See here where the core forms part of the multi-CPU "Matchbox Copro" as described here.
Udo writes up this development on this page.


Sun Mar 27, 2016 1:01 pm
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