Oldland is a 32-bit RISC CPU targeted at FPGAs. The main features are:

5 stage load/store pipeline.
16 general purpose registers.
N-way set-associative blocking instruction/data caches
Software managed instruction/data TLBs with 4KB page size.
JTAG debug controller for execution control and state modification/inspection.
Exception table for interrupts, data/instruction aborts, illegal instruction and software interrupts along with separate ITLB/DTLB miss handlers.
User and supervisor modes

There are three different simulators for the CPU:

oldland-sim: an instruction set simulator in C and is not cycle accurate.
oldland-rtlsim: an Icarus verilog simulation, models events but can be slow.
oldland-verilatorsim: a Verilator based simulation that runs > 1MHz and is cycle accurate.

The Icarus simulation is the most accurate and includes vendor models of the SDRAM whereas the verilator model does not model SDRAM timing or configuration.