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 Bitslice using currently available TTL 
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Joined: Mon Aug 14, 2017 8:23 am
Posts: 72
Hi All,

As technology moves on, many of the devices available to TTL designers have long since been obsoleted.

I recently looked at Brad Rodriguez's PISC cpu of 1994 and lamented that two of the key parts were no longer available.

https://bradrodriguez.com/papers/piscedu2.htm

The 74xx181 ALU and the 74xx172 register file are very rare and certainly not recommended for new work.

Whilst there are several innovations to replace the '181 with multiplexers and adders (Dieter Muller), I looked hard to find something that could readily replace the '172 register file.

Then I stumbled across at work, an old rack of drawers full of TTL, including the 74LS670 which is a 4 x 4 bit dual port register file.

A quick look at Mouser and Farnell confirmed that the 74HC670 is still available.

Now Dieter Muller's ALU is essentially a 4-bit slice, consisting of four 74xx153 multiplexers and a 74xx283 4 bit Adder - all in nice compact 16-pin packages, so this got me thinking of what else was available as a 4-bit part, in a 16 pin package, and the whole idea of a simple 4-bit TTL bitslice came into being.

Obvious candidates are the 74xx191 4-bit up/down counter which could be applied as an index register or a stack pointer.

Registers could singly be 74xx173 or a group of four in a 74xx670. Stacks can be fashioned from '670s too - should you wish to explore stack machines - which is on my to do list.

Additionally the 74xx194 4-bit universal shift register, which could augment an ALU with right and left shifting, and the 74xx85 4-bit magnitude comparator could be used for conditional branching operations.

Finally the 74xx161 is frequently used for program counters and incrementable registers.

So the plan is no more than 20 ICs, on a narrow pcb, forming a complete 4-bit slice. This puts 8-bit and 16-bit machines in closer reach of a modular construction.


Ken


Fri Aug 23, 2019 5:43 pm
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Joined: Tue Dec 18, 2018 11:25 am
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Location: Hampshire, UK.
Re: 74LS181; Criklewood Electronics appears to still have some.
https://www.cricklewoodelectronics.com/search.php?mode=search&page=1&keep_https=yes

There’s also an AliExpress vendor that seems to have some 74172.
https://www.aliexpress.com/item/33007181941.html?spm=a2g0o.productlist.0.0.257a2a88zUc0r6&algo_pvid=11e9223d-b1e3-4577-9b42-28f6c36b7846&algo_expid=11e9223d-b1e3-4577-9b42-28f6c36b7846-0&btsid=dcc8fb45-d333-4cdb-94f1-8b4a015fffe9&ws_ab_test=searchweb0_0,searchweb201602_9,searchweb201603_52
Very tempted to get some just to have a go at Brad Rodriduez’s PISC.

An experimental dual stack processor has on my to do list too, though I’ll probably be using AM2901s.


Fri Aug 23, 2019 7:48 pm
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Joined: Mon Aug 14, 2017 8:23 am
Posts: 72
B.

I realise that there are still some places where you can find the '181 (and even the '172) but for a viable project, I'd really be looking for major sources with 100+ pricing.

I like the idea of a bitslice, and having prototyped a 4 bit version on a breadboard, the move to a low cost pcb, is less of a leap of faith.

Brad Rodruigez has been synonymous with Forth and stack machines for more than 30 years - and the PISC as a learning tool has a certain attraction.

It's so easy these days to reach for a cheap FPGA board, or ARM capable of several hundred MHz - but I feel that lacks the purity of traditional TTL.

Nevertheless, FPGAs and ARMs are certainly cheap and useful tools to emulate and simulate experimental TTL processors that you lack courage to build for real.

Having built a Gigatron TTL computer from a kit, and stretched the clock to 12.5MHz, I'd like to have a go at a 16 bit machine, - either a Poorman's MSP430 or a true stack machine. The bitslice route seems to be the path of least resistance.

I'm open for suggestions and discussion if anyone else wants to have a crack at a low chip count project. I'm about to take a gap-year (aged 54) and looking for something to keep the grey matter ticking over.

I see that you are in Hampshire - I'm not too far away in Redhill, Surrey.


regards


Ken


Fri Aug 23, 2019 8:15 pm
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Joined: Tue Dec 18, 2018 11:25 am
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Location: Hampshire, UK.
Ah, I am only ever thinking of making one-offs for personal amusement. You have a very valid point when thinking of a production run.

Most impressed by the work Dieter Muller did investigating ALU designs, and the 74xx153/283 solution, no need for the 74xx182 look-ahead.

Often tempted to to try some FPGA/CPLDs and still have an unopened Mach4 starter kit from years back, but it’s just doesn’t quite have the same appeal for me as old TTL does.

The 74xx194 is a nice versatile chip, and I was thinking of using it as an Accmulator/Top Of Stack with a 74xx189 as the Next/rest of stack paired with 74xx670 for the PC/return stack. Until I discovered I had eighteen AM2901 4 bit slice chips in a “come in handy one day” box. So I might as well use them, it might be cheating a bit, but saves me a lot of TTL.

16 bits seems to me to be an easier size to design for, even though the chip count goes up.


Fri Aug 23, 2019 10:25 pm
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Joined: Mon Aug 14, 2017 8:23 am
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As an update to the proposed 4-bit bitslice design.

I found some 74F219 (16 x 4 bit RAMs), so I guess that's my register file sorted

I also revisited Wozniak's Sweet 16, and pondered whether this might make a suitable machine ISA to implement in TTL.

It simplifies the instruction set - as all register moves have to pass through the accumulator R0.

I have a bunch of '670 (4 x 4 bit RAM) devices to provide an address register structure.

I'm going to use Dieter Muller's ALU based on '153 multiplexers and '283 adder, (currently used in the Gigatron) but with the means to provide a right shift, which would fit nicely into the bitslice strategy.

I'm hoping that the detail will fall into place in the next few weeks so I can start prototyping the bitslice.

If I can create a simple 16-bit cpu design, based on 4-bit slices in under 80 ICs total - I will be very happy.

I'm looking for some discussion and feedback, if anyone else is interested in building a 16-bit TTL machine.

Ken


Tue Sep 03, 2019 4:59 pm
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Joined: Fri Mar 22, 2019 8:03 am
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Location: Girona-Catalonia
monsonite wrote:
I'm looking for some discussion and feedback, if anyone else is interested in building a 16-bit TTL machine.
Ken

Well, I'm certainly interested, so I will keep an eye on this for updates.


Tue Sep 03, 2019 10:02 pm
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Joined: Mon Aug 14, 2017 8:23 am
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Thanks for your interest Joan.

I just wish for a simple 16 bit architecture, which we can all discuss here.

Best

Ken


Tue Sep 03, 2019 10:33 pm
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Joined: Wed Jan 09, 2013 6:54 pm
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I'm interested too!


Wed Sep 04, 2019 7:38 am
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Joined: Mon Aug 14, 2017 8:23 am
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Hi Ed,

Thanks for your interest.

Having been inspired by the Gigatron, and it's approach to getting the most from a minimum architecture, I'm ready to take on a new challenge.

I've been following the thread over on the 6502.org forum, regarding a faster implementation of the 6502 in TTL - which has brought together some of the best of today's TTL computer designers including TTLWorks and Drass

http://forum.6502.org/viewtopic.php?f=4&t=5612

Whilst I'm not aiming for anything like the 40-50MHz machine that they are discussing, I would be quite happy with 10-20MHz - a speed dictated by the carry propagation time of the 74F283 adder used in the ALU.

Dieter Muller's ALU based on 74'153 multiplexers is an ideal candidate for the bitslice approach - consisting of 5 or 6 simple TTL packages per slice. Extending this to 16-bits is very manageable - and the sort of thing that can easily be transferred to a low cost pcb. The physical hardware need not be daunting either, I'm putting a rough cap of 80 devices on the overall design - so that's the sort of thing that can be built on a couple of Eurocards.

As this is very much a learning exercise for me and hopefully of educational value to the wider audience, I'm keen to extend the project to include the necessary software simulation, and support tools such as assembler, romulator and whatever else it takes to breathe life into the TTL design.

In a parallel thread, I'm expecting to model the architecture in verilog - in a similar way to the OPC series of machines were developed and characterised using FPGAs.

So, in the spirit of OPC, I'd like to pitch the project as a continuation of the OPC challenge - with the additional constraint of a TTL implementation that takes no more than a pcb (or pcbs) equal in area to a sheet of A4 paper. (210 x 297mm).


Wed Sep 04, 2019 8:27 am
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Joined: Mon Aug 14, 2017 8:23 am
Posts: 72
As an update to the bitslice design.

The Postman arrived this morning with a highly prized package of 74F219 16x4 RAMs.

I got these from LittleDiode - a supplier in South London who keep a lot of rare stuff.

https://www.littlediode.com/components/home.php

They are date-stamped 8818, and I am hoping that they are the genuine article.

To add to the mix, I have also happened upon some 74LS173 4 bit flip flops, some 74LS670 4x4 RAMs - which I intend to use as address registers and some 74LS191 4-bit up-down counters. These can be useful when used with the 16x4 RAMs to make a simple stack.

The logic design is starting to take shape, and I have started on a pcb design for the slice. As stated earlier the ALU will be almost identical to Dieter Muller's design that used multiplexers and an adder, with a 74xx194 shift register to provide shifting operations.

Much of the rest of the design is inspired by Marcel van Kervinck's Gigatron. I'm even thinking of ways that the bitslice cpu could act as a coprocessor to the Gigatron - with some shared access RAM.

I'm attending the Retro Computer Festival in Cambridge this weekend, with an opportunity to meet Marcel. I'm looking forward to meeting the creator of the ingeniously minimal TTL Gigatron.


Fri Sep 06, 2019 1:54 pm
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Joined: Wed Jan 09, 2013 6:54 pm
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I wish I could be there, but I have a diary clash. Maybe next year!

(There will be an ABUG event in Camberley on the weekend of 22/23/24 November - I'll be there, most likely. It's not unheard of to see non-Acorn projects underway there.)


Fri Sep 06, 2019 4:19 pm
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Joined: Mon Aug 14, 2017 8:23 am
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Ed,

Thanks for the heads-up. Camberley is not too far from me for at least a day trip.


Fri Sep 06, 2019 8:16 pm
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Joined: Wed Jan 09, 2013 6:54 pm
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Hope to see you there! Be sure to book a spot when the booking thread turns up. There should be space - it's a large venue - but it is the third time there and there's likely to be increased interest.


Fri Sep 06, 2019 8:59 pm
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Joined: Mon Aug 14, 2017 8:23 am
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I have now begun my sabbatical year - having left paid work yesterday afternoon.

I can now focus on my hobby projects, which include designing a 16-bit TTL cpu, learning verilog to familiarise myself with open source FPGAs and doing some more coding.

A friend suggested I look at "Digital" - an open source logic simulator very much like Logisim - which is now no longer supported.

https://github.com/hneemann/Digital/releases/tag/v0.23

Digital also supports FPGA development with HDLs supported. It seems that things are quickly moving on from Logisim days.

I have opened a new Githab repository for my bitslice design. At the moment its just somewhere convenient to keep the preliminary design sketches.

You can find it here: https://github.com/monsonite/Suite-16/b ... /README.md

Suite-16, my 16-bit project is a nod to Wozniak's Sweet-16. It's going to have 16 registers and a very similar ISA.

I have spent the day modeling the ALU and instruction decoder for the intended bitslice cpu.

I now have 8-bits simulated, running an incrementer or decremented in the accumulator, using either ADD or SUB instructions.

"Digital" has a large library of TTL and memory devices, and I found that after a few hours of using it - that it was quick and easy to hack logic together. Probably a lot faster than wiring a breadboard (with my fading eyesight).


Fri Sep 13, 2019 4:50 pm
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Joined: Wed Jan 09, 2013 6:54 pm
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Congratulations on starting your sabbatical! Hope to see lots of interesting developments.


Fri Sep 13, 2019 6:47 pm
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