I have been reading up a bit on the DLX recently and it seems to be a pretty nice RISC design.

What I haven't seen much of are actual implementations of it on some target platform. Do you know of any?

(And curiously I haven't seen much talk about adding caches, threading, multicores, extensions, and MMUs to it - something I would have expected to see a lot of as it is a popular student project base.)

It seems from this article that the DLX cpu is a teaching example found in a book(*) - is it open source and do you have a link to code?

But it turns out from this supporting website that

(which I probably should have known)

As it's a teaching example it seems reasonable that coding it up is left as an exercise to the student. Here's one take: http://www.cse.lehigh.edu/~caar/lou/dlx.html (with no copyright license)

Ed
(*) The article mentions: Peter J. Ashenden, The Designer’s Guide to VHDL, Second Edition. Morgan Kauffman Publishers, 2004.

Thanks for the link, though that one is not even pipelined!

It has been used for teaching cpu design for 15 odd years AFAIK, and for something that firmly embedded in academia one would expect to see a pletora of papers and student works that add features to the basic design.

I have been toying with making two additional instruction types for the architecture, but that is of course miles and miles away from something synthesizable... (hence my interest in something that already works to see if it can be crafted on to it if I can teach myself enough VHDL)

EDIT: And Wikipedia is as usual a great source of information http://en.wikipedia.org/wiki/DLX

Good point about wikipedia!

Here's another unlicensed codebase - looks like two weeks of a student project: http://code.google.com/p/riscymips/sour ... vn%2Ftrunk

Here's what seems to be a superscalar vhdl dlx (again, unlicensed):
http://www.rs.tu-darmstadt.de/downloads ... arDLX.html