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 Father and son build an 8 bit computer (Version 1). 
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Joined: Tue Dec 18, 2018 11:25 am
Posts: 32
Location: Hampshire, UK.
Fabian and Mark decided to build an 8 bit computer together.
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A number of years ago (2011), I thought it would be a good idea to share an electronics project with my son aged 10 at the time. We decided to build an 8 bit computer. I myself had doubts we would ever finish it, at best get a basic ALU going, but it was a good excuse to spend some productive time where we both could learn something together.

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It wasn't until late 2014 that we actually got the ALU soldered and working and that's where it was shelved....

About March of 2015 we developed the oscillator circuit....

By late 2015 we had it adding; subtracting, reading and writing by manually setting RAM addresses simply by enabling or disabling the necessary hardware.

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The design had many flaws... With the simple as possible concept in mind we kept the addressing and instructions at 4 bits given its basic functionality. The jump command was superfluous as the design did not include comparator circuitry such as zero, minus or carry flags, rendering it useless, but included the instruction nevertheless as the program counter had the option.

http://www.ruby-red.com.au/8bitmachine/Assets/version1/8%20bit%20movie.mp4


Tue May 12, 2020 2:26 pm
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Joined: Tue Dec 18, 2018 11:25 am
Posts: 32
Location: Hampshire, UK.
http://www.ruby-red.com.au/8bitmachine/#
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The journey continues with a much improved design simply named v2 (version 2). It's intention was to be a trainer machine and therefore it's architecture closely resembles that of v1, but with the following improvements - a complete rehash of the Control Matrix, 8 bit addressing, an additional C register, a 4 bit state register and a larger instruction set.

http://www.ruby-red.com.au/8bitmachine/Assets/version2/schematics

http://www.ruby-red.com.au/8bitmachine/Assets/version2/slides/20190906_144619.html

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With 8 bit addressing, v2 can access up to 256 bytes of RAM and has the capability to display numbers up to 65535 locally....
The 7 segment LEDs will output decimals from -32768 to 32767 for 2's complement, or 0 up to 65535 for unsigned integers, and has the capability of displaying HEX equivalents. Currently v2 contains 59 instructions up to a maximum of 256, and offers 16 states of micro code, unlike v1 who's Control Unit was purely one state per instruction. Memory and Data share an 8 bit bus with clock speeds varying from zero peaking around 2 MHz. It would have been interesting to have included a memory stack pointer, a shift register, and an interrupt controller, but we decided to leave these for v3, however register C was a neat alternative provided the code is not recursive or contains nested loops for the CALL and RETURN instructions.

http://www.ruby-red.com.au/8bitmachine/Assets/version2/prime.mp4
http://www.ruby-red.com.au/8bitmachine/Assets/version2/guess.mp4
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This design was developed with the 64k edition (v3) in the pipeline and will always be regarded as a learning tool, a stepping stone if you will, but v3 will have an entirely new architecture

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V2 incorporates an Arduino Nano acting as a serial monitor which in turn interfaces an SD card with the RAM module, a Bluetooth module and an additional Parallax Propeller board to connect a VGA monitor and USB keyboard.

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The assembler creates .lst, .bin, .cdm (Cedar Logic format) and Logisim simulator files, along with a binary file for each control ROM if required, all by the click of a button. Once assembled, the much coveted newly generated binary file can simply be written to the RAM chip via an SD card.


And there’s even a foldable cut-out model:-
http://www.ruby-red.com.au/8bitmachine/Assets/version2/cube.pdf


Tue May 12, 2020 3:03 pm
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1419
Excellent!


Tue May 12, 2020 7:02 pm
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Joined: Tue Dec 18, 2018 11:25 am
Posts: 32
Location: Hampshire, UK.
The journey continues ...
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After many hours of brain storming and research, version 3 is well on the way. We decided to build the new architecture on a Cyclone-V FPGA running at 8 MHz - potentially it will run faster.

Circuit schematic here:- http://www.ruby-red.com.au/8bitmachine/Assets/version3/schematics/
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In brief, v3 contains a 16 bit address bus, an 8 bit data bus, 64K of RAM, up to 256 Instructions for the Control unit, 16 special registers, Interrupt controller incorporating 16 Interrupt request ports, 256 byte memory stack, DMA controller and 256 I/O ports.

http://www.ruby-red.com.au/8bitmachine/
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During this time I have been writing a retro text based DnD game - reverse engineered for the v3 prototype. A game that we played back in 1984 on DOS based terminals during our college years, although Fabian was a far cry from being thought of at that time. I must say there has been a nostalgic comfort whilst writing this code, thinking that it will execute on my son's computer (of his design) that started purely as a thought experiment, a game that only ran on arguably powerful mainframes for the day, and now on a home brew machine that didn't exist just a few months ago, that I still don't completely understand and possibly never will.

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Strangely, I have written the code for the Java simulator based on the schematics, that represents the new computer architecture, but still have not fully grasped its potential, yet it runs just the same.

The game is currently running on the simulator to test out the instruction set, until Fabian finalises the disk routines on the Monitor program, the game files will then be transferred onto the final v3 hard drive, and will hopefully prove to become a sort of stress test for the new hardware.

I have a small video of the game below, bearing in mind that the game runs significantly slower on the sim, so the refresh rates are quite obvious, and yes the knight does fit through the dungeon door.

http://www.ruby-red.com.au/8bitmachine/Assets/version3/8bitmachinev3.mp4


Sat Jul 04, 2020 10:18 am
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