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 Designs that use multitiple ram accesses? Before page-mode 
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Joined: Thu Jan 17, 2013 4:38 pm
Posts: 53
The "normal" use case of ram was to read a single byte/word at a time. Multiplexing the cpu and video chip was very common in machines with a 6502, Z80, or 68000.

I'm wondering if there were designs that did multiple accesses but only setting up the pre/post handling once?
I know the ZX Spectrum did this to read out the colour memory though it gave it a convoluted addressing mode for it.

How much would be possible to gain by doing it as back to back 2/4/8 serial accesses instead of them all being separate?


Wed Apr 08, 2015 12:28 pm
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Joined: Wed Jan 09, 2013 6:54 pm
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I just checked Chris Smith's book "The ZX Spectrum ULA" and it says page mode is used: the video system fetches pixel data and attribute data from the same DRAM column. As you suggest, this saves time. (Not sure why your title says "Before page-mode" - perhaps you could clarify?)

So page mode should be very useful for sequential accesses, at the cost of some complexity. It seems that the 68000 doesn't have that complexity - it makes a full row and column access every time, according to http://patpend.net/technical/68000/68000faq.txt
Even with the 68020 it seems an external memory controller would be needed to arrange for so-called burst accesses - see http://www.textfiles.com/bitsavers/pdf/ ... N-0616.pdf

It's not so easy to create the optimum strobe timings though: the Spectrum uses both edges of the 7MHz clock and still needs to use gate delays to shift edges - that's a technique to be used only with great care, because the delays will vary across different devices, and voltage and temperature.

Edit: Acorn's Electron uses just 4 DRAMs and so every byte access requires two DRAM accesses - I imagine it uses page mode every time, for each pair. I don't know if it's any more aggressive when doing video refresh, but it probably could be. (If it happens that a scan line can be configured to start on any address, which I imagine a 6845 would allow, that makes it much harder and much less likely. But any alignment constraint on a scan line would allow for page mode accesses. I don't know much about the Electron's video configuration flexibility.)

The best possible result would be a doubling of memory throughput, I think. See
http://en.wikipedia.org/wiki/Dynamic_ra ... ess_memory


Thu Apr 09, 2015 6:20 am
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Ah, here's detail on the Electron - every access is indeed a pair:
"Access to RAM involves accessing four 64Kb dynamic RAM devices (IC4 to IC7, each providing two bits of each byte) using two cycles within the 500ns period of the 2MHz clock to complete each access operation."
http://hgweb.boddie.org.uk/ULA/file/tip/ULA.txt
All the edges are derived from a 16MHz master clock.


Thu Apr 09, 2015 9:20 pm
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Joined: Thu Jan 17, 2013 4:38 pm
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BigEd wrote:
Not sure why your title says "Before page-mode" - perhaps you could clarify?

That was perhaps not exactly what I meant - I was thinking about memory from before it was offered with burst modes meant for accessing sequentially. I think "FDM"(? can't remember the name or shorthand) might have been one of the first types that was common.

Thanks for the answers anyway. I just though it was such an "obvious" way to "cheat" yourself to more bandwidth that it is strange that it hasn't been used more.
I know some 'high-end' pc designs back in the day had interleaved memory, though I'm not exactly sure what that meant. Did they start accessing another set of chips before the previous had finished its access cycle?


Sat May 09, 2015 7:33 pm
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Joined: Wed Jan 09, 2013 6:54 pm
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I looked up DRAM tech, and found
http://en.wikipedia.org/wiki/Dynamic_ra ... PM_DRAM.29
I vaguely remember the possibilities of EDO and FPM around the time I had my first PC (a P75) but I can't remember whether or not my system could use them. As far as I understand it, even the oldest DRAMs had the ability to access within a page, and these modes were incremental advances on that. Once PCs got caches, the DRAM accesses would be cache line fills and spills, which fits very well with burst modes.

As for interleaved memory, yes, I think the advantage there comes from running concurrent accesses. Whether they could be started at the same time, or only started on successive cycles, I don't know. It's an old technique (like so many in CS) - some early machines like
http://en.wikipedia.org/wiki/CDC_STAR-100
CDC 6600 http://www.drdobbs.com/control-data-660 ... /184404102
and IBM's Stretch used it.

If you can run Java the simulations at http://williamstallings.com/COA/Animation/Links.html might be interesting.

Cheers
Ed


Sat May 09, 2015 9:51 pm
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Joined: Sat Apr 18, 2015 6:13 pm
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I'm using a 32bit 72pin Simm in X16 mode on a MC68340 design. The reasoning being that I can interleave each 16 bit bank separately and so shave a few nS off access times by not having to wait for precharge times .

Chris


Tue May 12, 2015 8:36 am
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68340, eh? Nice! :) http://www.freescale.com/files/32bit/do ... C68340.pdf

But can you elaborate on the Simm, please? I assume there are separate Row-Address-Strobe (RAS), Column-Address-Strobe (CAS) and Read/Write inputs for each 16-bit half, making the two halves entirely independent.

By "not having to wait for precharge times," do you mean RAS precharge? IOW, you're eliminating RAS and doing CAS-only (aka page-mode) accesses? Or would each half of the interleaved access have its own RAS & CAS (but with each half of the interleaved access on its own timing schedule).

Keep us posted on your project!

Cheers,
Jeff

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Tue May 12, 2015 10:23 pm
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There's a standard pinout for SIMMs which might help:
http://en.wikipedia.org/wiki/SIMM#72-pin_SIMMs


Wed May 13, 2015 8:29 am
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Joined: Sat Apr 18, 2015 6:13 pm
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Hi Jeff,

Yes thats the puppy.

As previously mentioned I have a Kiwi (Simon Ferber), its a great board but I'm a speed freak so I wanted to look at making it a fully 16bit machine I was most of the way through designing a 68000 daughter card with a full 16MB of DRAM that could shadow the system ROM into RAM but life got in the way and Steve Moody came up with a full 68000 version with his Ddriag.

I am now concentrating (when time allows) on a completely new design. The intention is to try to make it as compatible as possible with the Kiwi by making the hardware memory map configurable to mimic a Kiwi. Obviously it can't all be done in hardware so the creation of a set of libraries for graphics and sound that can be switched for the equivalent Kiwi libraries is needed then hopefully we can share a code base. I think producing a 'compatible' of someone elses project computer is highly flattering.

Dr Jefyll wrote:
But can you elaborate on the Simm, please? I assume there are separate Row-Address-Strobe (RAS), Column-Address-Strobe (CAS) and Read/Write inputs for each 16-bit half, making the two halves entirely independent.

By "not having to wait for precharge times," do you mean RAS precharge? IOW, you're eliminating RAS and doing CAS-only (aka page-mode) accesses? Or would each half of the interleaved access have its own RAS & CAS (but with each half of the interleaved access on its own timing schedule).


Yes to the latter. I have no plans to try to impliment page mode. I have a bunch of SIMMS ranging from 2MB to 64MB that have 4 CAS and 4 RAS signals. Reviewing the Micron datasheet http://www.pjrc.com/mp3/simm/datasheet.html it became apparant that I could split the SIMM into 4 banks by connecting together CAS#0 and CAS#2 and also CAS#1 and CAS#3 to give me the 16bit split and then the RAS#0 thru RAS#3 gives me the 4 banks. In theory I can pair the RAS lines and then have 1 half for odd words and the other for even words and each 16bit bank would have independant timing. My thinking is I won't have to wait for the RAS precharge (tRP = 40nS) while accessing the other word.

I'll post the specs of the project at some point.

Regards

Chris


Wed May 13, 2015 7:05 pm
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