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 Designing GPIO pins 
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Joined: Sat Jun 16, 2018 2:51 am
Posts: 27
How does one approach implementing GPIO pins in a homebrew CPU?

Suppose the design has a dedicated IO databus. And much like the Z80 and 8080, it can be written to or read from using IN and OUT commands. Can the IO databus be used for GPIO?

My design looks like this:
schem.png [ 5.97 KiB | Viewed 1177 times ]

Can this design be used for GPIO? What else is needed to enable a pin to be used as a GPIO pin? I've looked at how modern microcontrollers wire their pins, but I have no clue what the circuitry is doing. For example, this is what an Arduino (Atmega328p) pin looks like:
avr_alternatePortFx.PNG [ 72.93 KiB | Viewed 1177 times ]

The Wikipedia page on GPIO pins mentions that:
schmitt-trigger inputs, high-current output drivers, optical isolators, or combinations of these may be used to buffer and condition the GPIO signals and to protect board circuitry

I assume some of the circuitry in modern microcontrollers does this and hence the complexity. But for a barebones, user beware implementation, what can be omitted or rather what is the bare minimum required?

A common solution I have seen in homebrew computers is to outsource the IO handling to a microcontroller (for example this and this z80 based computers). However I want to integrate the GPIO pins to my CPU, not outsource.

Wed Sep 12, 2018 12:25 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 748
Location: Canada
The easiest solution is to use a chip designed for GPIO. One of my favorites is the 6522. Other than that, it’s best to buffer the I/O from the cpu using a latch for output (74x374) and a buffer on input (74x244). It ends up being three or four chips by the time controls for the buffer and latch are included. That solution will only give you raw access to I/O and any other timing control would have to be done with software.

Robert Finch

Wed Sep 12, 2018 11:01 am
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1074
Hi Quadrant, welcome!

That ATMega diagram is interesting, and may be worth studying. They will be trying to cope with all sorts of use cases whereas you might have only some specific use in mind.

That said, your circuit does look as if it needs some additions.

First, on the output side, you will probably want to continue to drive some output value even several microseconds after your output instruction has sent the value to the port. So you need some state to hold the value that you are driving.

Then, on the input side, you want to see what's being driven by the outside world, not just what the output side is driving, so you need a direction control register to hold the bit which says whether this pin is an I or an O at the moment.

Or, possibly, you can do the trick of only driving to a low value and relying on a pullup resistor, in which case outputting a 1 means the output stage is doing nothing and the input can read the outside world.

You'll see the Atmega has a couple of synchronising latches too: this is a good idea if the input value is going into something complex like a CPU. Do some searching on metastability if you don't already have the idea.

Wed Sep 12, 2018 1:29 pm

Joined: Sat Jun 16, 2018 2:51 am
Posts: 27

Thank you both for the replies! It helped immensely. After reading and rereading your comments, then rereading the Atmega datasheet, I was able to understand what the circuit is roughly doing. Here are my notes:
schematic2.png [ 3.63 MiB | Viewed 1152 times ]

And here is my revised barebones GPIO circuit. It has a latch for the output, and a "synchronizer" for the input as suggested. (Basically a trimmed down version of the Atmega schematic). What do you think?
gpio_schem_v2.png [ 2.61 MiB | Viewed 1152 times ]

Thu Sep 13, 2018 3:43 am

Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1074
Glad we could help! That annotated schematic is very helpful, and your revised circuit looks good to me.

Please do post more about your CPU - if you're blogging elsewhere, a link would be good.

Thu Sep 13, 2018 7:23 am

Joined: Sat Jun 16, 2018 2:51 am
Posts: 27
BigEd wrote:
Please do post more about your CPU - if you're blogging elsewhere, a link would be good.

Will do =). Currently trying to wrap up the beta version (which I realize in more ways than one is an oxymoron).

Fri Sep 14, 2018 2:09 am
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