Those interested in Forth-like machines might be interested in the KDF9 from English Electric:

Quote:

KDF9 in summary had the following features:

- Zero Address instruction format (a first?)

- Reverse Polish notation (for arithmetic operations)

- Stacks used for arithmetic operations and Flow Control (Jumps) and I/O using ferrite cores with a one microsecond cycle

- Separate Arithmetic and Main Controls with instruction prefetch

- Hardware Multiply and Divide occupying a complete cabinet with clock doubled

- Separate I/O control

- A word length of 48 bits, comprising six 8-bit 'syllables' (the precursor of the byte) [these syllables comprised a 2-bit field plus two 3-bit fields, coded in what was termed 'slob-octal' (syllabic octal) in which we became quite expert!]

- A 6-bit character set (plus 2 bits for parity, for I/O only!) which gave eight characters per KDF9 word

- Variable Length instructions comprising one, two or three syllables (thus the KDF9 word could contain six arithmetic instructions, two main store operations, three two syllable instructions or any mix): instructions could span word boundaries but a special compiler feature could force a new word if required

- The 48-bit word could contain the following arithmetic formats:

- one 48-bit fixed point (signed) number

- two half-length fixed point numbers

- half of one double-length fixed point number

- one 48-bit floating point number (39-bit fraction, 8-bit characteristic, 1-bit sign)

- two half-length floating point numbers

- half of one double-length floating-point number

- The 48-bit word could contain eight 6-bit characters

- Microcoded instruction sequences based on two interlaced clocks (P1 and P2) running at 1 MHz, a pulse width of 250 nanoseconds, the machine being 'synchronous', and a minimum instruction time of one microsecond

- A main store with a six microsecond cycle time (48 bits) up to eight times 4096 words with no parity! (equivalent to 196K bytes!)

- An internal register structure, consisting of a 16 word by 48 bit arithmetic 'stack', the 'Nesting Store', a separate 16-word nesting store for subroutine return addresses, a 16-word (the 48 bits organised as 3x16 bits) 'Q' store used for I/O and address modification operations [all quadrupled for the optional Time Sharing feature], all with a cycle time of one microsecond but NO parity!

- A physical technology using single sided printed circuit boards of approximately 6 inches by 8 inches, with 24 pcbs per 'bin', eight bins per 'rack', and two racks per 'cubicle'

- Use of high speed transistors, transformer coupled, diode-transistor logic [+ nor gates], several MAD (multi aperture devices) for complex logic conditions, diode matrix sequencers

- A typical pcb, the BIFF (flip-flop), four per board, using eight transistors and discretes, with 32 gold plated edge fingers

- As a rough approximation, 20,000 transistors per KDF9 system, and 2000 transformers (Polo sized toroids)

- A single phase Swinging Choke stabilised Power Supply generating ~750 amps at 5 volts +/-12v, +/-5v...

Notice that there was very little provision for lamps and indicators or any engineering aids.

All the above from the development story as told at

http://www.cs.man.ac.uk/CCS/res/res18.htm#cPhoto Gallery:

More in my post over on gplus:

https://plus.google.com/u/0/10704982391 ... 5nfBVBFNLi