Z80: has integrated memory refresh logic?
Apple II: Screen mode is organized so that a correct refresh of memory is done?

Does modern memory have "externally visible" refresh cycles, or are they internal only to the memory? (I.e. do you have to refresh it from some logic somewhere?)
How long are refresh cycles compared to regular read/write cycles?
If not for modern memory, then for vintage: Is any memory access good enough to refresh?
If yes, do any memory controllers detect access patterns and give the cpu/whatnot more access cycles if a refresh is not needed?
Are there any systems that do "double" accesses like the ZX Spectrum does with the bitmap and colour data? (It keeps either the column or row static between access 1 and 2.) (Does the Atari ST do something like this?)
Are there any systems(cpus?) that does interesting things with memory and/or refresh?

Wow. Some of these I can answer for you; let's see...

• Z80: has integrated memory refresh logic?
  Yes, the refresh register, R, increments each time the CPU fetches an opcode. Back in the day, this was a major boon. It cut costs by eliminating the need for an external multiplexer and a chip to count through the DRAM's row addresses. But several years later DRAM chips began to feature internal refresh address counters, rendering the Z80 refresh counter a non-issue.
  
  
• Apple II: Screen mode is organized so that a correct refresh of memory is done?
  That's certainly plausible (but I don't know for sure what an Apple II does).
  
  
• Does modern memory have "externally visible" refresh cycles, or are they internal only to the memory? (I.e. do you have to refresh it from some logic somewhere?)
  Go see what's out there on the market nowadays! The trend is to make DRAM products easier to use. For example a "pseudo static" RAM is really a dynamic RAM that includes support circuitry that lets it mimic the simplicity of a static ram.
  
  
• How long are refresh cycles compared to regular read/write cycles?
  They may be the same or they may be shorter. Depending on the strobes & R/W signal applied, a DRAM cycle can take several different forms. IIRC, one of them, the so-called RAS-only cycle, is comparatively short but is sufficient for refresh purposes. Not all computers necessarily use this, though. In the simplest designs, only two basic cycles are used (read and write), both full length and both updating the row address and the column address. It's an unsophisticated approach, but with many computer designs there would be no benefit in using anything fancier.
  
  
• If not for modern memory, then for vintage: Is any memory access good enough to refresh?
  Generally, yes -- any access is good enough. For example the DRAM can't tell the difference between a cycle whose data is used for video and a cycle whose data is fed to the CPU. And a RAS-only cycle isn't even a complete access; no data is fetched. But a CAS-only cycle (mentioned later) is useless for refresh because the RAS strobe is absent.
  
  
• If yes, do any memory controllers detect access patterns and give the cpu/whatnot more access cycles if a refresh is not needed?
  Clever idea! Probably that has been done. But the amount of extra hardware would largely outweigh the benefit. The DRAM only needs to spend a small percentage of its time refreshing, so it's hard to justify extra hardware that -- even if it were 100% effective -- could only slightly improve overall throughput.
  
  
• Are there any systems that do "double" accesses like the ZX Spectrum does with the bitmap and colour data? (It keeps either the column or row static between access 1 and 2.) (Does the Atari ST do something like this?)
  A CAS-only cycle is a speedy form of access that omits the update to the row address and only updates the column address. It's possible to do a long string of CAS-only accesses in sequence, so that could be described as double, triple, quadruple or whatever. It sounds like you're referring to a two-at-a-time sequence. I can't confirm whether that's the Spectrum and Atari do. Certainly there are other computers that exploit the CAS-only cycle. For example modern CPUs have caches, and a series of CAS-only cycles is a highly effective way to move a "burst" of data from DRAM into the cache.
  
  
• Are there any systems(cpus?) that does interesting things with memory and/or refresh?
  Sure! Sometimes the refresh is accomplished via software, for example a periodic interrupt that reads a sequence of addresses. Turning things around the other way, the Z80's refresh counter has been used for a variety of goals having nothing to do with refresh! http://en.wikipedia.org/wiki/Zilog_Z80

cheers,
Jeff

http://LaughtonElectronics.com

This is clearly not my field. Sounds like the time between required refreshes is much longer than I thought.

Off the top of my head, the penalty for refresh cycles is under 1%. But this seems to be wrong: As an order of magnitude, you need to go through all row addresses in some number of milliseconds. So that's 100's of accesses in some 1000's of cycles.

Concretely, 41256 DRAM chips need 256 refresh cycles every 4 ms. The 4116 need 128 refresh cycles every 2ms. At 1us per (full) access, which isn't what the Spectrum will be doing, that's 128/2000 or about 6%.

Referring to Chris Smith's excellent book "The ZX Spectrum ULA" it turns out that the Spectrum manages a full refresh in a little under 8ms, which is out of spec but appears to work. (The Spectrum uses 4116.)

Oh, and I read something on the Atari ST: They have a thing like an "MMU" (it manages memory accesses anyway) that acts like a kind of buffer so that the 68000 gets on and off the bus faster than if it was talking to the real memory.

(And IIRC the C= 64 does the memory refresh in the sideborder time - can't remember how many cycles it is.)

(I did a little looking up: on the PC, the penalty is 5.5% of cycles - see http://www.reenigne.org/blog/how-to-get ... m-refresh/ )
(You're right about the C64 - see http://www.zimmers.net/cbmpics/cbm/c64/vic-ii.txt)