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| Super vector processor http://anycpu.org/forum/viewtopic.php?f=17&t=486 |
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| Author: | robfinch [ Fri Nov 17, 2017 11:06 am ] |
| Post subject: | Super vector processor |
I've been toying with the idea of developing a superscalar vector processor capable of executing multiple vector instructions at the same time. I estimate it would take only about 15 million gates for a vector length 64. (I took the FT64 200k gates and multiplied by 64x as much hardware). I don’t know how practical it would be. The clock cycle time might be really slow. One application would be a spreadsheet like app with 64 independent lanes across horizontally across a grid. |
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| Author: | BigEd [ Fri Nov 17, 2017 12:42 pm ] |
| Post subject: | Re: Super vector processor |
So, that would surely be a multi-FPGA design? |
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| Author: | robfinch [ Fri Nov 17, 2017 7:10 pm ] |
| Post subject: | Re: Super vector processor |
It may be possible in a single FPGA chip. I found a 15 million gate device but not inexpensive and no free tools. Maybe time to try and crowdfund my "hobby"  I suppose I could do a proof of concept version with only 4 lanes (1/16 the size) and hopefully make the number of lanes a core parameter.
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| Author: | BigEd [ Fri Nov 17, 2017 7:15 pm ] |
| Post subject: | Re: Super vector processor |
Parameters are good! |
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