Came up with the following schematic for a bus master (not an interrupt) controller. I think it’s interesting that an 8259 could be used in this manner. I was going to use it to handle bus mastering, but decided to implement most of the circuit inside the FPGA chip to conserve board space. The 8259 has the option of rotating the interrupt priorities which could be put to use for rotating the bus master priorities. The 8259 receives a bus master request using one of it’s interrupt lines. It then generates an INT signal which is fed to logic that generates an INTA. The INTA pulses latch the resolved requester on the 8259’s cascade lines. The 8259 must be in master mode for this to work. The cascade lines are decoded and latched by a 74SLS259 and used as an acknowledge signal for the bus master. The ‘259 makes the bus master selection sticky. The 574 latch makes sure that the bus arbitration is on a bus cycle basis. (CYC goes high at the start of a bus cycle).
I think a circuit like this has a lot of good features. The bus master can be turned off by disabling the interrupt in the 8259. Priorities can be controlled via software.
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File comment: 8259 used to control bus mastering
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bm8259.png [ 29.2 KiB | Viewed 19133 times ]