Here's a project I was tempted to mention on 6502.org -- but it makes more sense to post it here!
dual 6809 single board computer.jpg [ 209.54 KiB | Viewed 5539 times ]
6809 computer block diagram.gif [ 15.95 KiB | Viewed 5475 times ]
As you can see from the diagram, this is a computer with two 1.5 MHz 6809 CPU's attached to a common memory array. The "master" CPU (on the left) runs the user application, and the "slave" CPU functions as a smart peripheral. Its main duty is to output memory data at high speed, feeding a video display.
No arbitration and no Wait States are required because the DRAM array is capable of 3 million accesses per second -- enough to fully supply the needs of two CPU's. In hindsight it seems strange that the memory is faster. It's such a conspicuous contrast with modern PC's, whose CPU's are far
faster than memory -- so much so that elaborate on-chip caches are the only way to avoid a horrific performance penalty!
Addresses for the video system are generated using a variation on the scheme made popular by Don Lancaster. This involves manipulating a CPU by disconnecting its data bus from RAM and sending it dummy op-codes -- essentially NOP's. In response the CPU produces an ascending sequence on its address bus, fulfilling a function like that of a DMA controller. For more detail please see the section, "Cheap Video and Lying To the Machine," here
The data fetched can be output as a character-oriented display or in bit-mapped mode. In bit-mapped mode, each byte fetched from memory contains four adjacent bit fields. Each two-bit field corresponds to one pixel on screen. The two-bit value acts as a lookup, selecting one of four gray-scale values stored in a 74_670 register file used as a "palette" RAM. The DAC is a simple weighted resistor network. In character mode basic ASCII encoding applies when bit 7 of the character is clear. Two options are associated with bit 7 being set. Either reverse video appears (courtesy of an XOR gate, not shown), or else custom characters are selected which have been uploaded to the RAM portion of the Character Generator.
Operating two processors from a single memory array involves some fancy footwork in regard to interrupt vectors. In order to provide vectors which are specific to each CPU, one CPU has the top portion of its address map slightly distorted. An XOR gate in address line A8 inverts that signal when the top 512 bytes of RAM are addressed. The effect is to exchange the 256-byte page at $FF00 with the page at $FE
00, from one CPU's point of view. Each CPU thinks its vectors are fetched from page $FF00 but -- like the phantom DMA controller mentioned earlier -- it's all done with smoke and mirrors!
I'm pleased to dust off this project (literally) and present it to the anycpu.org forum. The unit itself may be somewhat the worse for wear -- I notice quite a few IC's have gotten "borrowed" over the years -- and my memory of the details is spotty, but I'll do my best to answer questions if there are any.
edit: extra detail in diagram & texthttp://LaughtonElectronics.com