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Joined: Sat Feb 02, 2013 9:40 am
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After modifying the soc to use the amba bus, I decided to shelve it and stick with the WISHBONE bus.

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Robert Finch http://www.finitron.ca


Fri Jul 12, 2019 3:08 am
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Joined: Sat Feb 02, 2013 9:40 am
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Location: Canada
Thinking that maybe the uart woes are due to the baud generator which used a harmonic synthesizer, the baud generation was switched to use a clock divider. The baud reference clock is 200MHz so some of the higher baud rates are off by a few percent. It also isn’t practical to go beyond 921600 in an FPGA. Having changed the uart to support this I found out it didn’t make a difference. The baud rate was still off by a factor of about 8. Well, I finally checked the input clock to the FPGA and found that the input to the clock generator was set to 100MHz when it should have been 12 MHz. The whole system was running 8.33x too slow. It seems to work now. 6551 compatible uart.

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Robert Finch http://www.finitron.ca


Sat Jul 13, 2019 4:42 am
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Joined: Wed Jan 09, 2013 6:54 pm
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Hurrah!

Is the conclusion that WISHBONE is the simplest and best choice for educational use? Good to know.


Sat Jul 13, 2019 8:35 am
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 901
Location: Canada
Quote:
Is the conclusion that WISHBONE is the simplest and best choice for educational use? Good to know.

I’m not sure that it would be any better than the AXI bus, but it has fewer signals to it. I coded an AXI version of the soc and there seemed to be about 3x the code for bus interfacing, which maybe isn’t the best if one is trying to read through and understand things. In truth the AXI bus didn’t seem that hard to understand. It might be approachable by looking at one bus at a time because they all operate similarly. Some of the state might seem confusing to someone new though. Having separate read and write address busses with their own valid and ready signals is interesting. The bus is organized to support pipelined burst accesses. But what’s a pipeline again? What’s a burst access?
If building a system with a gui tool it may not matter how complex the bus really is, if it’s abstracted well. But when one starts to look at details…. And try and convince an interested student not to look at details…
WISHBONE has its own set of complexities. It too can support burst accesses. It was designed to be a “free” bus, no license required. It can be simplified to “send out an address and data and wait for an ack back”.
I liked the MOS 65xx/68xx bus for simplicity. “Send out address and data” assume it works. A simple synchronous bus is maybe the easiest to understand.

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Robert Finch http://www.finitron.ca


Sun Jul 14, 2019 3:42 am
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Joined: Wed Jan 09, 2013 6:54 pm
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Thanks - good points all! I had a quick look at AMBA and AXI and I begin to see what you mean! Good to see that they are open standards though. Very many years ago we used a valid-hold interface, which seems to be logically the same as AXI's valid-ready, but with a bit of additional cognitive load (hold being not-ready) that turns out to be unnecessary. This was at Inmos, and AFAIR the idea came from a chap who came from Anamartic. I wonder if there's a direct inheritance along the line.


Sun Jul 14, 2019 6:53 am
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