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Joined: Sat Feb 02, 2013 9:40 am
Posts: 1105
Location: Canada
Started this cpu yesterday as a one-page challenge cpu. It's about 80 lines of code. Instructions are single cycle except for memory loads (two cycle minimum) and jumps (two cycles).
Code:
// 16 true/false predicate registers, predicate 0 is always true
// 32 integer registers, 1 link register
// 24-bit code addressing / 32 bit data addressing
//
// {RR}:   pppp 00010 ttttt aaaaa bbbbb oooooooo
// ADD:      pppp 00010 ttttt aaaaa bbbbb 00000100
// SUB:      pppp 00010 ttttt aaaaa bbbbb 00000101
// AND:      pppp 00010 ttttt aaaaa bbbbb 00001000
// OR:      pppp 00010 ttttt aaaaa bbbbb 00001001
// XOR:      pppp 00010 ttttt aaaaa bbbbb 00001010
// MUL:      pppp 00010 ttttt aaaaa bbbbb 00001011
// SHL:      pppp 00010 ttttt aaaaa bbbbb 00010000
// SHR:      pppp 00010 ttttt aaaaa bbbbb 00010001
// ASR:      pppp 00010 ttttt aaaaa bbbbb 00010010
// RET:      pppp 00010 00000 ----- ----- 10000000
// NOP:      pppp 00010 00000 ----- ----- 11101010
// Cxx:      pppp 00010 -PPPP aaaaa bbbbb 1111oooo
// ADDi:   pppp 00100 ttttt aaaaa nnnnnnnnnnnnn
// ANDi:   pppp 01000 ttttt aaaaa nnnnnnnnnnnnn
// ORi:      pppp 01001 ttttt aaaaa nnnnnnnnnnnnn
// XORi:   pppp 01010 ttttt aaaaa nnnnnnnnnnnnn
// LD:      pppp 10000 ttttt aaaaa nnnnnnnnnnnnn
// ST:      pppp 10001 sssss aaaaa nnnnnnnnnnnnn
// ADDIS:   pppp 1001n ttttt nnnnnnnnnnnnnnnnnn
// JMP:      pppp 10111 l aaaaaaaaaaaaaaaaaaaaaa
// Cxxi:   pppp 11ooo oPPPP aaaaa nnnnnnnnnnnnn
// A ton of compares including a generate carry into predicate register
CEQ, CNE, CLT, CGE, CLE, CGT, CLTU, CGEU, CLEU, CGTU, CCRY, CODD

I'm planning on stealing the one-page OPCxx assembler with suitable modifications written in python.
While the constant field is only 13 bits, 32 bit constants can be loaded using the ADDIS (add immediate shifted) instruction which adds a 19 bit constant to the upper 19 bits of a register.
I chose to use 32 registers and a 3r instruction format to make things easier for a compiler. The result is a little larger cpu.

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Robert Finch http://www.finitron.ca


Wed Mar 25, 2020 2:48 pm
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1384
Interesting development - thanks for starting a thread!


Wed Mar 25, 2020 5:24 pm
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Joined: Mon Oct 07, 2019 2:41 am
Posts: 85
DO reg 0 and 1 return 0 and 1?
RISC machines remind of micoded machines internal ALU.The CMOS PDP 8
had a panel mode. I was thinking a similar idea could be used where a system call
would vector to a fixed rom area. The PC would be latched rather than stacked
and a small bank of scratch registers would swap in. Register indirect would refer
to the original registers. floating point might be done this way or OS functions
The fixed rom would not be cached,but run at the same speed as the core memory.


Thu Mar 26, 2020 9:53 pm
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 1105
Location: Canada
Quote:
DO reg 0 and 1 return 0 and 1?
Reg 0 always returns a zero. Reg 1 is general purpose.
Quote:
The fixed rom would not be cached,but run at the same speed as the core memory.
I've taken to including the boot rom (which is high-speed in an FPGA) as part of the L2 cache so it doesn't get cached at the L2 level. It feeds L1 directly. I think this kind of thing was done with the DEC Alpha.
I've kinda put this project on hold, to continue with Thor2020 instead. It's all really the same gigantic home project anyway, or so it seems at times. Thor2020 is going to be used as a processor for the ISA PC hopefully.

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Robert Finch http://www.finitron.ca


Fri Mar 27, 2020 5:01 am
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