Compare instruction formats and 2r1w instructions formats were worked on today. Instructions may specify the operation size 8,16,32 or 64 bits for integer instructions and the size of a constant (10,50,90, or 130) bits independently. The odd constant sizes are due to the use of 40-bit instruction words coupled with the ability to encode up to 10 bits in the 2r1w instruction. The constants will be extended or limited to the operation size.

An instruction may for instance specify a 90-bit constant but only a 32-bit operation which would allow the upper constant word to “hide” an instruction.
The 2r1w formats may substitute a constant for either register. There are also instructions that directly support a constant field of 20-bits, assuming one register (Rs1) and one constant are in use.

Branches are going to be based on a bit test of a vector from a compare result. The compare result is stored in a GPR. There will also be branches able to branch based on a register value or 0 (false),1(true),<0 or >0. The branch displacement is 20 bits.