Worked some on the reservation stations and bypassing networks. The bypassing networks are not shown on the pipeline diagrams as that would clutter up the diagram.

Reservation stations queue up to four arguments for up to three instructions. The argument values are set from the register file or from the bypassing networks. There are at least four bypassing inputs (parameterized). The current design has eight inputs.

Four of the bypassing inputs come from the input to the register file. This trims a clock cycle off of register access time. The other four inputs come from the outputs of frequently used functional units. For instance, the output of the first simple arithmetic unit (SAU) is bypassed back to its input so that back-to-back instructions can be made single cycle. It also feeds the input to other functional units.

The reservation stations are set up to be generic in nature. The same component is used to support different functional units. While the stations support up to four instruction arguments, all types of instructions (functional units) do not need that many arguments. The hardware for unneeded arguments will get trimmed by the synthesizer.

*****

Used up eight opcodes for SIMD support. Also, it was decided to move the precision field out of the branch format and into the opcode. This caused eight more opcodes to be used. But gives two more bits for the branch displacement.

To support lower precision non-SIMD operations the upper bits of the destination register are set to zero.

There are about 24 opcodes left open.

Some work on extended precision arithmetic. Added an ADC instruction that adds three source operands and produces low order and high order (carry bit) in two destination registers. A 256-bit add can then be done with just four instructions.
Format: adc Rd1, Rs1, Rs2, Rs3, Rd2

Shift instructions where also added that save the upper or lower bits of the shift result in a second destination register.

Added some more conditional move instructions. Conditional move if even (CMOVEVN), move if less than zero and move if less than or equal to zero.

Decided to get rid of the ADDnUI instructions. I cannot see them being used that often and the same functionality is available using a regular ADD_ASL instruction by substituting an immediate for Rs2. It is a little bit less code dense. It is probably worth it to simplify the instruction set.

Here is a table of the root opcodes:

Changed the PUSH and POP instructions from being implemented with micro-code to being implemented using the micro-op translator. PUSH and POP are now translated into one to five micro-ops depending on how many registers are used. There is less overhead and better performance of the operations when translated to micro-ops.

Changed the base data-path width to 128-bits which I am going to try and see if it will fit.

There are now 128 logical registers available in Qupls. It turns out that the BRAM setup is 512 registers deep no matter whether there are 32,64 or 128 registers. So, may as well make them available.