Got around to synthesizing the core by itself and running timing analysis on it. The clock is 100 MHz, and the timing reports that there is about 2ns slack. Meaning the clock could be faster (about 125 MHz). I think this is about the same timing as it had with the busses triplicated. However, once the core is placed in a larger system, the FMAX is lower. Note there is an issue of 5ps or less on the hold timing, but not enough to worry about. (The core seems to work).

interesting, thanks

The immediate mode instructions were accepting a byte operation on an address register; however, the address register would not be updated. This has been switched to an illegal op. This would not be an issue except for hand generated code.
Bug fix:
For the ADDQ / SUBQ instructions only long words were supported for address registers. This should have been both word and long word forms. For word operations the register would be updated without extending the low order word.

Refactoring
Moved setting of the condition code register flags out to its own module. This was a major modification.

Enhancements
The second major modification was to add a bank instruction prefix allowing the selection of up to 32 registers for an instruction. The BANK prefix contains a simple two-bit extension for corresponding register fields in the following instruction. It works slightly differently than the BANK prefix of the Apollo core.

Additions
Added a bank prefix for floating point (co-processor) instructions. Works the same way as BANK except applies to register fields in the float instructions.
Added a source two SRC2 prefix instruction. This prefix fetches a second source operand for the following instruction. This allows the ALU instructions to be of a 2 source 1 destination form which is popular for compilers.

Note the SRC2 prefix acts like its own independent instruction except that interrupts are not allowed between the SRC2 and its following instruction.
There may be both a SRC2 prefix and a BANK prefix before the following instruction.