Looking good!

Ignoring money, lost in building prototypes, and use of TIL311 displays, I am guessing the cost
would be about the same as the 8008 mark 8 computer in 1974,adjusting for inflation
.
While TIL311's where out in 1973's,A cheaper design might have used nixie tubes, or standard 7 segment displays.
PCB size looks about the same as the MARK-8, but it has 256Kb ram compared to the 256 byte ram
of 1974. Modern memory has come a long way from back them.

Sadly the use of 68B50 ACIA limits my clock speed to 2 MHZ,and the bootstrap has no room to spare
for use of other serial chips. A new design may give me a 3MHz clock, but then timing is rather critical.

The new mother board is in and the computer is running so far with the 99 bottles of beer program.
Made some changes with the bootstrap loader, a tad smaller.

Trying out a new version of microcode, now that my 12 Mhz oscillator arrived.
(.666 uS clock. 1.333 uS memory cycle.)
I need to rebuild the memory/IO boards now with the proper bypass caps,
.22 uF rather than the .15 uF ones.
Now to let the Komputer burn in.
Ben.

Decided to revise the memory PCB, mostly because I had a bunch of tiny mods to make.
Going back to more standard parts, 74LS14,74LS189,74LS04, for the ALU card, thus timing
changes. Now .750 uS cycle with a 12 Mhz clock or a .630 uS cycle time with 14.2 Mhz osc,
thus a baud clock is needed from the CPLD.
Timing is now MOS memory rather than CORE, so a few instructions run 1 cycle faster.
Now to wait two weeks for the new board to arrive.

MOS memory timing unstable.
Gone back to core memory timing, with changes for the VMA memory
strobe. 1.25 (1.3) uS memory cycle now *CORE 1974*

Crashed mid test, then ran ok over night.
Removed the 8 pin socket, and hard wired in the 12 Mhz osc
for 1.5 uS core timing. retesting now. Hopefully the slower speed
will make it better for the power supply.
Ben.
PS The BCL Molecular II was 1.6 uS. 17 bit + parity



.

Juggled things around to get scaling x 2 , lea and a slightly different subroutine call.
Around 103 macro cells now, for the control CPLD and 83 macro cells for the ALU CPLD's.
testing over night, again.
Planning a bootstrap high level language in C, so the hardware changes are to make better
code generation. This I hope will let me get a simple file system up and running but the
bios stuff needs to be re-written in the HDL language. More Algol like than C.

The revised memory/io card is burning in now. Shortened traces where possible, and minor changes for bug fixes.
Boiler plate code for the new programing language is in, about 500 lines of code
with about 1 statement per line.
About another 500 lines to process code.

Testing with no fan. 39C room temp.
.75 uS Crashed with with garbage characters on the serial port.
1.0 uS ran the test ok. 45C
.92 uS running the test now. 45C.
Ben.