Hi All,

I've been working on a new computer, called the Isetta TTL computer.

It will be built from TTL chips. Most important features:

- runs 6502 instructions
- runs Z80 instructions
- 6.25 MHz clock (160nS cycle time) [ edit: this is now 12.5 MHz ]
- integrated 320 * 240 VGA color graphics, 64 colors
- 80 column text mode
- 512 kByte RAM ( 8 bit wide )
- 24 bits wide microcode in 3 flash chips

Details can be found here: https://hackaday.io/project/190345-isetta-ttl-computer

Most instruction have microcode now, for Z80 this includes:
- IX, IY instructions, EXX
- LDIR and CB-group instructions
- Overflow testing

Not implemented (yet?)
- 6502 decimal mode, BRK, RTI
- Z80 IO instructions, DAA, LDDR
- Z80 parity

Current status:

- Javascript simulation runs 6502 basic, 8080 basic and Z80 basic
- Hardware design almost completed, pcb design partly done (KiCad)
- On the Hackaday page, schematic and microcode is not the latest version

I want to keep the chip count low, so several features are handled by microcode, accepting the fact that some
instructions will use one or more extra cycles. Some design decisions were:

What it does have in HW:
- The familiar 8-bit ALU, built from multiplexers and two 74AC283 adders
- Include 16-bit program counter (PCH/PCL)
- Have a 16-bit data pointer (DPH/DPL)
- Have CGL (constant generator) on lower address bus (6 bits, from microcode). This also addresses the registers that are in RAM.
- Have an Accumulator and T (Temp) register. T register enables RMW calculations while accumulator is not changed.
- There are 16 pages of microcode. On-the-fly change of instruction set is possible.
- Each opcode addresses a series of 16 microinstructions.
- The microcode has a 3-bit code that determines which 64kB RAM section is addressed
- Hardware flags for N, C, TC (internal carry).
- Support for video generation

What it does not have in HW:
- No hardware 6502 registers X, Y and S. These are in RAM (outside regular 64K). Almost all Z80 registers are in RAM.
- No hardware shifter. Right shift is done with a table in RAM (outside regular 64K). Left shift by adder.
- No direct path from datapointer or program counter to ALU. But the upper or lower address bus can be routed to
the databus to access these registers, or access a constant from the CGL.
- No 8-input gate to determine Z condition. Instead, the byte result is saved to a special RAM location to be used later.
- No overflow-flag calculation.The 3 input bits for this calculation are saved to a special RAM location to be used later.
- No buffers for loading/storing the flags from/to the databus. This must be handled one-by one by microcode.

If this succeeds, it might be the first Z80-capable homebuilt TTL computer (I have never seen a Z80 TTL computer on the web,
except for FPGA based designs).

I suppose you will have questions...

Roelh

This is excellent! And loads of flexibility.

If you are saving the result byte to defer testing zero, doesn't that (and maybe a table) also cover what is needed for deferred parity?
Hope you remember 6502 BIT instruction reflects N=B7,V=B6 from B input rather than the discarded AND result, saved to defer zero.

Hi Ken, yes this could also be used to determine parity. But there is a complication in the Z80, there is a single flag for parity and overflow. I would have to store if the last calculation was logical or arithmetic, to determine if a jump is on parity or on overflow. For the moment, I don't use parity. Both Altair 8080 basic and TRS80 basic are working well in my simulation, so I don't need it now.
Several weeks ago I calculated the gate delays, and with a few changes it seems possible to clock the CPU at 12.5 MHz ( 1/2 VGA ). And with a few other changes, some IC's can be removed. I'll soon write about it on Hackaday.

Hi All,

Several changes were made, it should now be possible to run the cpu at 12.5 MHz cycle speed. See my logs on Hackaday.io:
https://hackaday.io/project/190345-isetta-ttl-computer

The design, based on SMD chips, fits on a 119 x 150 mm pcb.

The PCB was ordered today !

enjoy the hacking,

Roelh

A major milestone was reached today ! The original Apple 1 BASIC, programmed by WOZ, is running on the real
Isetta hardware ! It runs on the intended 12.5 MHz (80nS cycle time).

Details are here: https://hackaday.io/project/190345-isetta-ttl-computer/log/229087-the-real-hardware-runs-apple-1-basic

A lot more to do, a few things:

- Getting VGA output to work
- Make a simple file system in the 32Mb serial flash
- Get PS/2 keyboard working

Any suggestion for a very simple wear-levelling file system for my serial flash ?

Any suggestion for a very simple wear-levelling file system for my serial flash ?

Have a cpu with 2 seral flash cards, then you can just copy from one flash to new one every so often,

Well done Roelh!

Is there really a need for wear-levelling? The datasheet mentions 100k program-erase cycles per sector.
https://www.mouser.com/datasheet/2/949/ ... 489574.pdf

(I wonder if you could monitor write times and erase times to see if the device is getting old?)

But to answer the question, I searched and found a couple of wear levelling filesystems - it would be good to hear from anyone with experience
https://github.com/pellepl/spiffs
https://github.com/littlefs-project/littlefs