Going back to more 1968 style computer. Word addressing. Accumulator design rather a register to register design.
Subroutine calls on even bountry, and single word 19 bit addressing. This way I can use CALL theading for threaded code. 8 registers including
the PC.
More inspection of the new oder code, conficts with some other decoding,thus I am back to two word calls and the orignal order code.

Moving clock generation to the ALU card as well. The ALU gets to use the master clock first.
Moving up to 1984, with a 1.5 uS memory cycle time -- ram . A 1977 version 1.8 uS core or ram.
PS: Looking at the chips I have, I may tweek it for 150 ns ram, and add a wait state for IO.

Gone back to a hex format.
The schematics are roughed out, but no layout is done yet. This will be a emulated design with stubbed IO
routines, for the next few months. Getting close to a "hello world" type test program.
PS: Last minute addition - signed bytes (10 bits).

Changed from Big Endian to Little Endian, so I can read and write disk blocks on the PC and port over to Compact Flash
later. Disk IO would be a modified IBM patter drive from 203 tracks to 225 tracks. 4Kb per track like the PDP-8, 10 bit bytes, GCR. Some sort of strange fat system.
Now I need a name for this beast, and time for software.