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The next design - a octal 20 bit cpu http://anycpu.org/forum/viewtopic.php?f=23&t=1112 |
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Author: | oldben [ Thu Apr 04, 2024 7:32 am ] |
Post subject: | The next design - a octal 20 bit cpu |
Going back to more 1968 style computer. Word addressing. Accumulator design rather a register to register design. Subroutine calls on even bountry, and single word 19 bit addressing. This way I can use CALL theading for threaded code. 8 registers including the PC. More inspection of the new oder code, conficts with some other decoding,thus I am back to two word calls and the orignal order code. |
Author: | oldben [ Thu Apr 11, 2024 6:09 am ] |
Post subject: | Re: The next design - a octal 20 bit cpu |
Moving clock generation to the ALU card as well. The ALU gets to use the master clock first. Moving up to 1984, with a 1.5 uS memory cycle time -- ram . A 1977 version 1.8 uS core or ram. PS: Looking at the chips I have, I may tweek it for 150 ns ram, and add a wait state for IO. |
Author: | oldben [ Sun Apr 28, 2024 5:42 am ] |
Post subject: | Re: The next design - a octal 20 bit cpu |
Gone back to a hex format. The schematics are roughed out, but no layout is done yet. This will be a emulated design with stubbed IO routines, for the next few months. Getting close to a "hello world" type test program. PS: Last minute addition - signed bytes (10 bits). |
Author: | oldben [ Mon Apr 29, 2024 5:55 am ] |
Post subject: | Re: The next design - a octal 20 bit cpu |
Changed from Big Endian to Little Endian, so I can read and write disk blocks on the PC and port over to Compact Flash later. Disk IO would be a modified IBM patter drive from 203 tracks to 225 tracks. 4Kb per track like the PDP-8, 10 bit bytes, GCR. Some sort of strange fat system. Now I need a name for this beast, and time for software. |
Author: | oldben [ Sat May 11, 2024 8:47 pm ] |
Post subject: | Re: The next design - a octal 20 bit cpu |
I have the emulator printing "Hello world". I got dosbox-x running and cross compiling small c version 1.2. I need to write a simple FAT file system ( 8 inch floppy 10 bits/byte GCR single sided) and the small C libs. System setup 462 Kb per floppy, two floppies per system. 48K ram + ROM BIOS + 2 serial at 1200 baud? about 1976. |
Author: | oldben [ Sun May 19, 2024 10:32 pm ] |
Post subject: | Re: The next design - a octal 20 bit cpu- NOT |
I have improved the design, since I could only find 18 bits, in the bit bucket. This is a serial design, 3 bit nibble. The only rare parts are a 13 mhz osc, CY7C122 (256 x 4 ) 25 ns ram and a 74H74. 2.5 uS memory cycle time. Operate 2.5 uS auto 5.0 uS index 7.5 uS The emulator will print "hello world", but more testing needs to be done. Ben. |
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