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 EPiC - A new 68k multi-processor motherboard project 
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Joined: Wed Apr 24, 2013 9:40 pm
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Location: Huntsville, AL
On page 13-2 of the User's Manual, there's a table which defines the EVDD/EVSS pins as pertaining to the output drivers, and the IVDD/IVSS pins as pertaining to the internal logic of the part. I could find no specific definition of the VCC (VDD) pin voltage other than the datasheet defines VCC as +3.3V±5% when defining the other signal parameters.

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Michael A.


Wed Jul 09, 2014 2:39 am
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Garth wrote:
I can't find anything at all in the data sheet telling what these are, that is, what the difference is between EVDD and IVDD which would be power, and EVSS and IVSS which would be ground.


Yeah, but I just don't get why they put a positive and a negative in the same group. I would think the center text would read:

xx EVDD / IVDD
xx EVSS / IVSS


Last edited by mercury0x000d on Wed Jul 09, 2014 3:28 am, edited 1 time in total.



Wed Jul 09, 2014 3:14 am
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MichaelM wrote:
On page 13-2 of the User's Manual, there's a table which defines the EVDD/EVSS pins as pertaining to the output drivers, and the IVDD/IVSS pins as pertaining to the internal logic of the part. I could find no specific definition of the VCC (VDD) pin voltage other than the datasheet defines VCC as +3.3V±5% when defining the other signal parameters.


Okay, that makes a little sense... it seems they separated the power supplies used for internal logic and switching and for external output driving so that, if you have an unusually large amount of fan-out (or high drain components to drive) then you can supply more power to the output driver pins than the internal logic pins.



Does that sound plausible to you guys? If that's the case, that's a pretty cool way to increase the chip's versatility.


Wed Jul 09, 2014 3:26 am
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Then it sounds like EVDD would be 5V and IVDD would be 3.3V. As for the different grounds, I expect it's to keep the outputs' current from going through the internals' ground connections' inductance and causing voltage drops there that could effectively shift the input thresholds. Keeping them separate until they reach the ground plane would help keep the internals' reference closer to real ground.

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Wed Jul 09, 2014 4:01 am
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edit: oops, posted to explain the Internal / External thing. Then deleted it, noticing it'd already been covered. :oops:

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Wed Jul 09, 2014 4:39 am
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Garth wrote:
Then it sounds like EVDD would be 5V and IVDD would be 3.3V.


Sounds good to me! That's what I'll plan for, then. :)



Garth wrote:
As for the different grounds, I expect it's to keep the outputs' current from going through the internals' ground connections' inductance and causing voltage drops there that could effectively shift the input thresholds. Keeping them separate until they reach the ground plane would help keep the internals' reference closer to real ground.


Also, with less voltage swing from high to low on the internal logic, this would help the processor achieve faster switching speeds, yes?


Wed Jul 09, 2014 5:48 am
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mercury0x000d wrote:
[Also, with less voltage swing from high to low on the internal logic, this would help the processor achieve faster switching speeds, yes?

I'm not sure that was one of the reasons to go to lower voltages. I remember hearing in the mid-1980's that they were talking about going to voltages lower than 5V because they were predicting that die feature sizes would reach such small dimensions that 5V plus the overshoot from bad terminations for example would actually punch through. In the late 80's, there was the push to lower voltages because charging MOSFET gate capacitances to a lower voltage meant less charge in coulombs, and that, multiplied by the lower voltage, meant that the power used was proportional to the square of the voltage, so a 3.3V system could operate at less than half the power of the equivalent 5V system. However, if the parts are optimized for 5V and not 3.3V, they won't go as fast on 3.3V, because transistors won't be saturated as well, depletion layers in the FETs will be thinner which leads to more capacitance, and time constants are much longer when you effectively increase both the R and the C. If the R and the C were constant though, the RC time constant is the same regardless of voltage.

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Wed Jul 09, 2014 6:06 am
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As an FYI, the latest FPGAs like to the run the cores at very low voltages: 1.8V, 1.2V. But the I/Os typically are able to run at 3.3V. So having two separate supplies is a necessity. But as we've said, even if the two rails are the same voltage, separate decoupling will help.

(In fact FPGAs also have rules about how many outputs should be allowed to switch simultaneously, given various groupings of I/Os and various choices of signal slew rates. Just having some pins and a power supply doesn't mean you can do anything you like.)

(To respond to your points Garth, I think the drive for lower voltages is both for power management and to allow for thinner oxides at smaller denser geometries. Once you have the thinner oxides, you don't have the luxury of running at high voltages any more. The gain in decreased power dissipation is substantial, as you say, and that allowed for faster clock rates and greater transistor counts.)


Wed Jul 09, 2014 6:17 am
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Good to know. I might get the hang of this electronics thing yet! :)

I was verifying the pins in the pinout diagram, and it says there are 34 IVDD / IVSS pins... but I count 35. Multiple times. Maybe I just miscounted... idk.


Wed Jul 09, 2014 7:43 pm
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Garth wrote:
Then it sounds like EVDD would be 5V and IVDD would be 3.3V.


I don't agree with this assessment. In Table 12.1 on page 12-1 of the User's Manual, the absolute maximum supply voltage is specified as -0.3V to +4.0V. I believe that for the 68060, EVDD and IVDD are both +3.3V. There are some inconsistencies in the nomenclature, e.g. VDD vs VCC, but I am of the opinion that this is a single voltage +3.3V processor, and not a dual voltage processor. That specification also indicates to me that the processor is not +5V tolerant.

One reason for defining the VCC/GND signal pairs as they are as EVDD/EVSS and IVDD/IVSS is to indicate that if multiple/split planes are used, then put paired signals on the same planes. I would expect this technique to minimize the potential differences between the portions of the chip powered by the different power pin pairs. It is very likely, given the number of metalization layers available at the time on the chip that independent power/ground pairs were needed on the chip. Inductance issues on the pins, coupled with the independent powering of different sections of the chip, may lead to ground bounce issues that require low impedance power sources (which can be provided by additional power planes) for the internal logic and the output drivers.

Without further information, in the form of a layout guide, I would probably recommend that a very robust power and ground planes be used.

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Thu Jul 10, 2014 12:01 am
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I realize it could be wrong, but this indicates the processor is in fact dual-voltage... I don't know what to think at this point. lol


Thu Jul 10, 2014 12:44 am
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A year or two ago I just threw out a big box of loads of 68K materials, including 68060, from the late 1980's and the 68060 stuff from the 90's. It had loads of data sheets on processors and peripheral ICs, ap. notes, sales literature, and probably other things I'm forgetting. It had been collecting dust for 20 years and I figured I'll never use it. Now I wish I had kept it for you.

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Thu Jul 10, 2014 1:41 am
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The introduction of the User's Manual (from the Freescale website) makes the following statement:
Quote:
Although the MC68060 operates at a lower operating voltage, it directly interfaces to both 3-V and 5-V peripherals and logic.


I went looking through the electrical specifications, and in Table 12.4 "DC Electrical Specifications. (VCC = 3.3V ± 5%)", the input High voltage is defined as ranging from 2 V (min) to 5.5 V (max). That will probably indicate, contrary to my previous statement, that the external signal inputs are 5V tolerant. That would be a good thing for your project.

The quote from the User's Manual above reinforces my opinion that EVDD and IVDD are a single voltage. My recommendation is not to assume that EVDD is +5V. Nothing in the User's Manual supports that interpretation. Perhaps further research is required. At this point, I would proceed with caution. I would be more inclined to trust the Preliminary electrical specifications of the User's Manual rather that the "Technical Data" in the referenced Wikipedia article you linked to.

I am only trying to dissuade you from connecting +5V to EVDD without additional confirmation. I would suggest that Motorola's use of a single lower operating voltage for this processor was driven primarily by concerns over power dissipation. The power dissipation values given in the User's Manual are not something to sneeze at. Just the processor dissipates more power than the FPGA-based cards that I design and work with on a regular basis.

My cursory review of the User's Manual leaves me thinking that it would have been a very nice processor to design with. It's unfortunate that the same level of R&D was not applied to its ISA as was applied to the x86 by Intel, AMD, Cyrix and others. The 68020+ processors have always been a better liked ISA than the x86.

Good luck with your project. Looking forward to reading about your progress here.

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Thu Jul 10, 2014 2:06 am
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Might it be worthwhile to locate and study the schematics of some working '060 hardware? A superficial web-search didn't immediately pan out for me, but I probably didn't get my search parameters dialed in correctly.

Best wishes,

Mike


Thu Jul 10, 2014 4:37 am
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From the User's Manual:
Quote:
11.2.1 Power Considerations

The MC68060 operates at a supply voltage of 3.3 V, not 5 V. The MC68060 interfaces gluelessly to transistor-transistor logic (TTL) levels.

I wouldn't recommend trying to build this into a 5V system though - there are notes about managing the power-on rampup, and also notes about the TTL-compatible I/O that sound like complications well worth avoiding.

Cheers
Ed


Thu Jul 10, 2014 7:35 am
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