These canned oscillators are probably a good choice. A fixed divider should be sufficient - note that the final output driver may need to have specific edge rates, so check your CPU datasheet. These oscillators are not very close to 50% duty cycle, so if you're close to the max speed of anything you will need to at least divide by two to get an even mark-space ratio.

So you're saying I won't be able to reliably get more than 50 MHz out of these?

You could reliably clock a 50MHz system by dividing by two.

But with a 40/60 spec on the duty cycle, the 100MHz output would need to be driving a 125MHz system to be safe. If you tried to drive a 100MHz system you'd probably have trouble because one of the clock phases would be too short.

(There might be systems where the duty cycle of the clock doesn't matter)

Ohhh, okay, I see.

On a related note, I did find out there is such a thing as running too slowly, although I'm sure this is nothing new to you guys. lol It never occurred to me that this could even be a possibility. You can imagine my surprise when my new 10 mHz 68000 hung when I gave it a 1 kHz clock: all the address lines simultaneously gained in voltage until they reached logical high, then went low and stayed there. On 4 and 8 mHz, it runs fine.

Speaking of unsurprising, we-told-you-so announcements (lol) I had little positive progress while the site was down. I got a pair of EEPROMs burned containing a small assembly program which initializes the DUART then sits in a loop continually broadcasting a character repeatedly down the serial line. I wired up the components and threw the power. And of course, it didn't work. Applying my logic analyzer, I can see dozens of spurious pulses throughout what was otherwise a clean, perfectly synchronized address bus. Oh, interference! Why must you plague me so?

At this point I either buy a bunch of wirewrap equipment, redesign the breadboard using rigid wires and form them into straight runs similar to PCB traces or just move the whole thing to a PCB. I think I'm going with the latter. I searched a PCB design houses and - lo, and behold! - there's one right here in town! Talk about convenience! I've been using Fritzing to create a basic schematic which I'll post for you guys' review.

A 10 mHz (ten milli-Hertz, or .01Hz) 68000 would be severely overclocked at 1kHz. (m=milli, M=mega.)

The NMOS 6502 had a minimum recommended speed of 100kHz, as going much below that could make registers start losing data. The CMOS 65c02 allows stopping the clock indefinitely though, without losing data.

Hi Mercury
so you did run some 68k code from your EEPROMs? Even if unsuccessful, that's good progress. Do you have enough bypass capacitors? You need capacitance close to each chip, as well as enough capacitance in the power supply itself.

Cheers
Ed

I guess it would! Note to self: don't screw up the Roman numeral prefixes lol
Speaking of overclocking, this 10 MEGA Hz (lol) 68000 ran fine at 16(!) MHz... for about 7 seconds. Then it was time to dance the ol' reset two-step lol



The NMOS 6502 had a minimum recommended speed of 100kHz, as going much below that could make registers start losing data. The CMOS 65c02 allows stopping the clock indefinitely though, without losing data.[/quote]

That's a pretty cool feature. Wish the 68000 had that! As enamored as I am with Motorola's processor, I must say I am fairly impressed by the technology behind the 6502. It seems they put a ton of optimizing into it... now if only they made a 32-bit superscalar version! lol

Ehh... I think so? It was hard to follow along on the logic analyzer due to all the interference, but I gather that the chip did manage to run several bytes of instructions before the interference upset the address bus to the point of causing weird memory accesses and crashing the CPU. I probed the one EPROM and did in fact get bytes back out of it appropriate to the addresses I was manually poking into it, so that's at least one good thing.

My assembly code is as follows:



I think (hope?) that should do the job.

A somewhat simpler test could be to remove all chips that can drive the data bus (except the CPU of course) and hard-wire the bit-pattern for a NOP on it. On the simpler 8-bit machines with which I'm familiar, this is a safe and easy test, and it allows you probe the address lines to see if they're acting like an expensive binary counter. I'm not aware of any dangers in trying the same test on a 68k system, but I should caution you that I have no direct hands-on experience with 68k hardware at such an intimate level.

Mike

You're referring to the "free-run" test. I can personally verify that such a thing does work on the 68k. In fact, it's almost like the "Hello World!" of the 68000 universe lol

I tried this on my system and it does in fact drive a series of LEDs in proper binary sequence, but when the address bus is under logic analyzer-grade scrutiny you can see the blips and jolts of bus interference. Attempting to fix this, I'm in the process of drastically rewiring my breadboard to see if I can shorten up the leads and tidy the connections to eliminate this problem.

Oh! Sorry, Ed, I didn't answer your question earlier. Yes, I have bypass caps at the supply lines for every IC.

I got a crazy idea... I wonder if a length of tinned wire wrapped around all the members of a bus and connected to ground would cut down on crosstalk? May be worth a shot...

It won't really have the desired effect, as each signal wire will have as much inductive coupling and more capacitive coupling to the neighboring signal wires it is bundled with than it does to the added ground wire. If you could twist a ground wire with every individual signal wire, and ground the second wire at both ends to the ICs the signal wires go to, then you'd have a balanced pair that would be much better behaved-- and that's what the Cray-1 did. It's kind of prohibitive though. The links on the first page tell a lot about what's going on up there in fast-edge-rate land.

I'm about a third of the way through drawing up a schematic for the dev board and I've been doing a lot of looking into PCB fab prices and procedures. In my research, I've come across folks saying that to get high speed (above 16 to 20 MHz) you have to use a 4-layer PCB. Would you guys agree? And has anyone here done any successful high speed (in the 1xx MHz range) designs?

I don't agree, at least not exactly. Without 4 layers, success will depend on a high level of skill -- and probably also on knowledgeable use of some extreme or unorthodox techniques. In that sense the assertion is true -- that, assuming unexceptional skill level, you do need a 4-layer board.

Example of an unorthodox technique? The main one would be adding jumpers on one or both sides of the 2-layer board. This relieves routing congestion, and gives you a better shot at the goals of producing a good Gnd/Vcc layout, and assuring a multiplicity of paths for signal-return current flow. Jumpers could be in the form of either surface-mount zero-ohm resistors or short lengths of solid wire which you manually apply, making sure they hug close to the surface of the 2-layer board. (Labor intensive!) Really the jumpers are just an alternative -- and more difficult -- means of producing 4 layers of routing.

So, the 4-layer board starts to look like money well spent! It increases your chance of success, while reducing your design time and construction time too. BTW did your cost survey include oshpark.com? I seem to recall their 4-layer process wasn't that much more expensive than 2-layer.

cheers,
Jeff

Okay, good info. It sounds like the dev board will hum away just fine at its 10 MHz on a two layer, but I think I'll go ahead and do four layers for the '060 version. According to this, a four layer board contains power and ground planes. So one would connect the grounds from all components into the ground plane (along with any connections which need permanently grounded or logic low-ed) and hook all the positive supply lines (along with any connections which need to permanent be logically high) to the power plane and then the routing of all the signal carrying traces (address and data buses and chip enable / control lines) gets done on the outer top and bottom layers, correct?





Yes, I looked into them as well. Right now they're in my favorites due to their price (although for the dev unit's simple two layer board Fritzing's fab house comes in a bit cheaper) and a local house due to their location. I haven't talked to them yet, but I'm hoping they can give me some good pricing since we won't have to do any shipping or what-have-you.

Speaking of the dev board's two layers, what are your thoughts on me making the component side double as a ground plane and run power and signals on the solder side?