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EPiC - A new 68k multi-processor motherboard project http://anycpu.org/forum/viewtopic.php?f=23&t=135 |
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Author: | mercury0x000d [ Sat Jun 21, 2014 1:54 am ] | ||
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project | ||
The clock pulse generator arrived and - as you can see below - generates a nice simple stream of pulses. I measured it accurate to within a few thousandths of a MHz at 4 MHz. Not bad!
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Author: | Dr Jefyll [ Sat Jun 21, 2014 2:13 am ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
Looks good! But you need to get in the habit of bypassing the supply, with cap's located close to the IC. Another good habit -- since I'm already nagging you anyway! -- is to keep the windows on EPROMs covered. Obviously those in the photo aren't in active service. But later when they are in use, be aware that photoelectric effects can upset their operation. It's not that ambient light will erase them, but they can temporarily go wonky if not kept in the dark. Voice of experience talkin' to ya! -- I got bitten by this once before someone warned me. Quote: I measured it accurate to within a few thousandths of a MHz -- Jeff |
Author: | mercury0x000d [ Sat Jun 21, 2014 3:26 am ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
Dr Jefyll wrote: Looks good! But you need to get in the habit of bypassing the supply, with cap's located close to the IC. Thanks! And I'm not sure what you mean by bypassing... Bypassing the power supply? Wouldn't that short things out? Forgive my electrical newbness lol Dr Jefyll wrote: Another good habit -- since I'm already nagging you anyway! -- is to keep the windows on EPROMs covered. Obviously those in the photo aren't in active service. But later when they are in use, be aware that photoelectric effects can upset their operation. It's not that ambient light will erase them, but they can temporarily go wonky if not kept in the dark. Voice of experience talkin' to ya! -- I got bitten by this once before someone warned me. Hey, I appreciate your "nagging"! lol I'm far from an electrical engineer, and I need all the help in that regard as I can get! But yeah, I had no idea they were that sensitive. I shall keep my electrical tape at the ready then! Dr Jefyll wrote: Just a reminder to always question your instruments and assumptions. The slight inaccuracy you noticed is as likely to arise in the meter as in the oscillator. Or it could be a bit of both. In the latter case the meter could read 4.000 and still be slightly wrong. -- Jeff I was wondering that myself, if the variance was in the chip or the meter. After all, it is a bargain basement Radio Shack model! But the website where I found the chip did say it's normal for it to have a slight (less than 1%) fluctuation. I think it's actually a PIC of some sort running code to bit bang a clock signal? I'm not sure. But that would explain the variance. |
Author: | Dr Jefyll [ Sat Jun 21, 2014 3:50 am ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
Quote: I'm not sure what you mean by bypassing... Bypassing the power supply? Wouldn't that short things out? The cap goes in parallel with the supply pins of the IC, and yes it's a short but only for high frequencies, not for DC. Another way to think about it is to say the capacitor is a reservoir that stores a charge. That helps "smooth over" those instants during which the IC's current consumption instantaneously spikes (which is normal). Current for the spike is locally supplied by the cap. Otherwise the spike would try to draw current all the way from the power supply, inches away (which is unacceptable -- especially for VLSI such as a 68060 !!! ). |
Author: | Garth [ Sat Jun 21, 2014 5:20 am ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
Dr Jefyll wrote: Otherwise the spike would try to draw current all the way from the power supply, inches away (which is unacceptable -- especially for VLSI such as a 68060 !!! ). and the problem with that is that even a short piece of wire has substantial inductance for the fast rise times involved. When you switch the logic state of one or more outputs at a fast slew rate, the fact that it has to charge up the bus capacitance causes a sudden change in the supply current or ground current; and that rate of change, multiplied by the wire inductance, gives the voltage drop across that wire. It's bad enough in the Vcc line, but imagine the ground pin suddenly being above ground by two or three volts! That causes problems in several ways, including momentarily changing input thresholds, also effectively flipping other output states that were supposed to remain stable, and that the ringing double-clocks things too fast for the circuit to respond without erroneous results. Fast ICs of any size have many power and ground pins since having so many parallel connections reduces the inductance. On something like a memory IC in SOJ package, you'll find the power and ground connections at the middle of the sides instead of at the corners, the purpose being of course to give the shortest connections to power and ground. All of this won't help much though if the connections on the outside are not done correctly. One thing that helps of course is the bypass capacitor across each IC, with the connections between the capacitor and the IC as short as possible. This problem, which did not exist back when we only had 1MHz processors, is why hobbyists are not designing big projects with high-speed parts. It can be done, but it's a different world. Do read my page on avoiding AC-performance problems in your construction, at http://wilsonminesco.com/6502primer/construction.html, and follow the links. Someday I'll figure out how to illustrate certain transmission-line phenomena to add to that page, things I seem to be at a loss to know how to draw effectively, and I have not found suitable pictures online to use. Somewhat related is the page on expansion buses and interfaces, at http://wilsonminesco.com/6502primer/ExpBusIntrfc.html, and to a lesser extent, the page on answering wire-wrap questions and doubts, at http://wilsonminesco.com/6502primer/WireWrap.html. A few decades ago, a lot of engineering students went into digital thinking they would avoid some of the analog complications; but as digital got faster and faster, it not only became analog, but the worst kind of analog-- RF! |
Author: | mercury0x000d [ Sat Jun 21, 2014 4:47 pm ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
Ahh, I get it now. You mean I should add a cap across the IC leads to smooth out the supply to the chip. I've noticed that done on some boards at work and now it makes sense! I'll have to add that into my final high speed design. The pulse generator outputs 5 different clocks - 1 Hz, 1 KHz, 4 MHz, 8 MHz and 16 MHz. I'm running the breadboard mockup at only 1 KHz for now, but once I get a board designed I'll change the pin connection on the clock to run at the full 8 MHz. Garth wrote: ... Fast ICs of any size have many power and ground pins since having so many parallel connections reduces the inductance. ... I've always wondered why the 68060 pinout lists like two dozen power connections! Also, that explains why modern microprocessors have that array of surface mount caps directly under the socket! I swear I learn something every time I talk to you guys. So far the final tester board (which I'm coming to call the dev board) specs will be as follows: CPU: Motorola 68000 @ 8 MHz RAM: 8 MB SRAM ROM: 1 MB EPROM with custom bootloader and BIOS firmware RTC: ICM7170IPG Ports: 2 x PS/2, 1 x Infrared, 1 x Serial Glue: 74LS series logic chips Also, on a side note, I've had it with these cheap little breadboard power supplies!! One tiny short and they're never the same. The first I had started supplying 12 volts(!) to my breadboard upon getting shorted, and the one I have now only outputs 2.40 and 2.97 Volts instead of 3.3 and 5 Volts. Come on! Thankfully I had nothing connected to them and was just testing them out. I'm going with a small USB Micro B adapter to supply power from now on. At least I know if that gets shorted the worst that will happen is my computer shutting down. Don't ask me how I know that... |
Author: | mercury0x000d [ Sat Jun 21, 2014 5:03 pm ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
Garth: Would these be sufficient to smooth the supply lines to the ICs? |
Author: | Garth [ Sat Jun 21, 2014 6:06 pm ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
mercury0x000d wrote: Garth: Would these be sufficient to smooth the supply lines to the ICs? They're not bad for the application, but I will make some comments. I'm probably going overboard here, as some of the comments won't matter yet at low-speed digital bypass applications, but it would be good to start thinking about them for later, to get into good habits for when it really makes a big difference.
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Author: | mercury0x000d [ Sat Jun 21, 2014 9:35 pm ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
Thanks for the pointers! Something like these perhaps? |
Author: | mercury0x000d [ Sat Jun 21, 2014 9:53 pm ] | ||
Post subject: | It works! ...I think. | ||
Well... it seems like the breadboard works thus far. I hooked everything up in open loop mode, grounding the data bus and holding the necessary signals in the appropriate manner, and fired up my makeshift power supply. On my meter (which is the best I can do until my shiny new Saleae arrives) I get the logic state alternating once every 8 seconds or so at 4 MHz at address line 23. Moving down to line 22 I get the same thing, but it alternates in roughly half the time as line 23. I move to line 22 and the trend continues until around about one third of the way down the bus when the slew rate gets too fast for the meter to pick up. So... it seems the address bus is counting as it should! Not bad for an afternoon. Also, I was surprised I could get the thing to run (if it is in fact running! lol) at 4 MHz. I may still have to drop it down as the design gets more populated, but it works for now. Warning: Some of you wire wrap guys will probably get a headache from looking at the attached picture... you've been warned! lol
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Author: | Garth [ Sun Jun 22, 2014 2:51 am ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
mercury0x000d wrote: Thanks for the pointers! Something like these perhaps? From the info that's there (including the small pictures farther down), it looks like they fit the bill. I went to the Mouser catalog and site, and wow, it looks like we're losing the economy of scale on these things as everything goes to surface mount, because the cheapest I could find was these, at $.03 each for 1000. I know we weren't paying that much ten years ago, yet most of the .1's Mouser has are considerably more. |
Author: | Garth [ Sun Jun 22, 2014 7:15 pm ] |
Post subject: | Re: New 68k motherboard project |
Garth wrote: The transmission-line behavior comes into play with fast rise times, and slowing the clock down does not by itself remedy that. Leaving longer between edges does give time for ringing to die out which helps on things like address and data lines; but the clock lines still have to be done right if the rise times (or slew rates, or edge rates) are fast, or things won't work. If you heed the things on the page I pointed to, and the links there, you'll be fine. One of them is the 6502.org forum topic, "Techniques for reliable high-speed digital circuits," at http://forum.6502.org/viewtopic.php?f=4 ... 664#p17664. At http://forum.6502.org/viewtopic.php?f=4&t=2029&start=46, Ed just added a great post to the "Techniques for reliable high-speed digital circuits" 6502.org topic, with a link to a video showing on a high-end oscilloscope how the ringing trouble is relative to rise times, not clock rate, and Jack Ganssle makes good comments there, like about well established circuit-board designs no longer working when the IC manufacturer increased the slew rates (ie, cut the rise times, making them faster), even though the clock rate was unchanged. I've experienced a similar thing myself. At the moment, there are two posts after that one. Be sure to read them. |
Author: | mercury0x000d [ Mon Jun 23, 2014 5:20 am ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
Once again, Garth, thanks for the good info. I haven't even gotten the project off the ground yet and I'm already learning so much stuff. |
Author: | mercury0x000d [ Sat Jun 28, 2014 1:14 am ] |
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project |
I hooked a series of LEDs to the address bus and confirmed the processor is indeed running as it should! As soon as my ATX power supply breadboard adapter comes in, I'll power the board back up and post a pic or two. |
Author: | mercury0x000d [ Wed Jul 02, 2014 3:54 am ] | ||
Post subject: | Re: EPiC - A new 68k multi-processor motherboard project | ||
Okay, it's update time! My Saleae 16 channel logic analyzer came in as well as my bypass capacitors and ATX power adapter. I've finally got the dev board running off ATX power (no more cheap breadboard power supplies!) and the address bus is functional as expected. It seems when you feed the CPU directly off a PSU, the initial period of voltage instability messes things up for a bit. I'll have to implement a circuit which doesn't let power flow to the rest of the board until line 8 of the ATX PSU is high (the Power Good signal) to try to eliminate that. I do see a slight increase in stability after adding the bypass caps, and it's probably only a slight difference due to the fact that I can't get them very close to the CPU whilst on a breadboard - or at least whilst on the breadboards I own. Next up: once my new batch of breadboard wires comes in, the address decoder goes in place.
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