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 Thor Core / FT64 
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 1076
Location: Canada
Started porting the code updates from nvio back to FT64. There were a lot of changes in the past couple of weeks so there’s a lot to update. While FT64 remains basically a 64-bit machine, floating-point will use double-extended or 80-bits precision. That means wider internal busses. The core will also be altered to use address generators rather than the alu’s to generate addresses.
The implementation language is being switched to System Verilog. Newer versions of files are .sv files.

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Robert Finch http://www.finitron.ca


Sun Jun 16, 2019 2:54 am
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 1076
Location: Canada
Got the data cache and write buffer ported back and widened the internal busses. Then ran a simulation to confirm nothing was broken.

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Robert Finch http://www.finitron.ca


Mon Jun 17, 2019 3:17 am
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Joined: Sat Feb 02, 2013 9:40 am
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Location: Canada
Improved some of the documentation for FT64. Working on the NVIO doc I realized that there was a better way to organize the book. The instructions are described by functional unit rather than all being lumped together.

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Robert Finch http://www.finitron.ca


Tue Jun 18, 2019 4:06 am
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Joined: Sat Feb 02, 2013 9:40 am
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Location: Canada
Worked on FT64 today.
FT64 is so out-of-date. It’s a year a behind on edits to the superscalar engine.
I decided to try and pipeline the instruction decompression better. It requires an additional decompression queue before the main issue queue. At the moment I have the decompression decompressing to the issue queue but that won’t work without a lot of changes. The issue queue expects the register values to be ready to queue which isn’t the case if the instruction isn’t decompressed yet. Without additional pipelining there's a lot of logic between the instruction cache and issue queue. The core must lookup the cache line, align it for 16-bit addressability, then figure out where the second instruction is, then determine instruction lengths, then decompress the instruction, then feed it to the right fetch buffer. Yikes! that's a lot to do in 1 clock cycle.

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Robert Finch http://www.finitron.ca


Fri Dec 13, 2019 4:42 am
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