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 FT68000 - 68k similar core 
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 918
Location: Canada
I haven't done much more on this project. Instead I've taken up writing a sci-fi story which is taking up more of my time.


I had a brief look at floating point support. I've written some FP primitives but they have limited pipelining so they use a slow clock. I really should go back and add more pipelining to increase the fmax.


I'm backtracking on the mailbox implementation. It's questionable to connect every mailbox to every sender in parallel. I think it would be slow because of all the routing. So it's back to having a message queue in the router component.

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Robert Finch http://www.finitron.ca


Tue Jun 26, 2018 5:18 am
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1225
> SF story
Interesting - hope we get a chance to read it one day. Does it involve a rogue CPU?


Tue Jun 26, 2018 8:22 am
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 918
Location: Canada
Quote:
Interesting - hope we get a chance to read it one day. Does it involve a rogue CPU?

The story involves an immortal woman escaping from a planet about to be fried by the star. Sorry, no rogue CPU in the story. There is only limited AI in the story. Takes place in about a 1990 technical level, with one or two exceptions.

I’ve written about 11,000 words over the last two weeks. It’ll likely be a year or so before the story is done.

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Robert Finch http://www.finitron.ca


Wed Jun 27, 2018 1:15 am
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Joined: Wed Jan 09, 2013 6:54 pm
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It's a huge amount of work, I know that - but not from personal experience. Good luck with the endeavour!


Wed Jun 27, 2018 7:12 am
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Joined: Sat Feb 02, 2013 9:40 am
Posts: 918
Location: Canada
Added states to support floating point to FT68000x16.v. While the 68000 supports several different operand types (single, double, long, word, byte, etc). The FT68k will only support doubles (64 bits) to begin with. There is some finagling of the datapath necessary as the FT68k previously didn’t support data over 32 bits.

Used an unused mode, reg combination of the 68k (mode 7, reg 6) to implement reading of 64-bit immediate constants. Immediate constants are handled slightly different in FT68k. Rather than look at the op size, there is a separate mode, reg combination to support encoding 16, 32, or 64-bit constants. This allows longer operations to make use of shorter constant encodings. It does make the required instruction encodings not 100% binary compatible, but very close. Since FT68k is little endian constants are encoded differently than the 68k anyway.

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Robert Finch http://www.finitron.ca


Fri Jun 29, 2018 4:11 am
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Joined: Sat Feb 02, 2013 9:40 am
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Location: Canada
Now that I selected multiple mode,reg combinations to represent immediates, I've decided that was a bad way to do things and to change it all around and use just a single mode,reg combo. This came from a desire to support extended precision (96 bit) arithmetic. Instead the immediate values are going to be processed with bit 15 of a 16 bit parcel indicating to include more bits in the constant (0 means include the next parcel). The problem is that so many different sizes of constants are required. I want to be able to support at least 128 bits and lower. 128 bits take 9x 15 bits. A small constant (less than 16 bits) will have bit 15 set to indicate that is the last parcel required. I'm going to modify the core so that addresses and displacements work the same way.

I came up with an extended precision (96 bit format) for the FPGA makeing use of 18x18 multipliers.

Attachment:
File comment: 96 bit FP format
DXPres.png
DXPres.png [ 8.09 KiB | Viewed 2810 times ]

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Robert Finch http://www.finitron.ca


Sat Jul 07, 2018 6:01 am
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