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 A RISC-V design for FPGA, with SoC & OS, and in a novel HDL 
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1258
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"A FPGA friendly 32 bit RISC-V CPU implementation" by Charles Pappon
https://github.com/SpinalHDL/VexRiscv
Quote:
  • RV32IM instruction set
  • Pipelined on 5 stages (Fetch, Decode, Execute, Memory, WriteBack)
  • 1.16 DMIPS/Mhz when all features are enabled
  • Optimized for FPGA
  • Optional MUL/DIV extension
  • Optional instruction and data caches
  • Optional MMU
  • Optional debug extension allowing GDB debugging via an openOCD JTAG connection

(As it's a RISC-V, there's a GCC already.)

Real time OS:
https://github.com/Dolu1990/FreeRTOS-RISCV

Novel HDL:
https://github.com/SpinalHDL/SpinalHDL
Quote:
SpinalHDL is a programming language to describe digital hardware and then generate the corresponding VHDL/Verilog file.
  • No more endless wiring. Create and connect complex buses like AXI in one line.
  • Reduce code size by a high factor, especially for wiring. Allowing you to have a better visibility, more productivity and fewer headaches.
  • Free and user friendly IDE.


Fri Jul 21, 2017 8:57 pm
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Joined: Wed Jan 09, 2013 6:54 pm
Posts: 1258
Another open free RISC-V implementation: PULPino.
http://www.pulp-platform.org/

Via the comments on a Hackaday article on homebrew CPUs.


Sat Jul 22, 2017 4:44 pm
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