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A RISC-V design for FPGA, with SoC & OS, and in a novel HDL http://anycpu.org/forum/viewtopic.php?f=23&t=420 |
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Author: | BigEd [ Fri Jul 21, 2017 8:57 pm ] |
Post subject: | A RISC-V design for FPGA, with SoC & OS, and in a novel HDL |
. "A FPGA friendly 32 bit RISC-V CPU implementation" by Charles Pappon https://github.com/SpinalHDL/VexRiscv Quote:
(As it's a RISC-V, there's a GCC already.) Real time OS: https://github.com/Dolu1990/FreeRTOS-RISCV Novel HDL: https://github.com/SpinalHDL/SpinalHDL Quote: SpinalHDL is a programming language to describe digital hardware and then generate the corresponding VHDL/Verilog file.
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Author: | BigEd [ Sat Jul 22, 2017 4:44 pm ] |
Post subject: | Re: A RISC-V design for FPGA, with SoC & OS, and in a novel |
Another open free RISC-V implementation: PULPino. http://www.pulp-platform.org/ Via the comments on a Hackaday article on homebrew CPUs. |
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