|A RISC-V design for FPGA, with SoC & OS, and in a novel HDL
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|Author:||BigEd [ Fri Jul 21, 2017 8:57 pm ]|
|Post subject:||A RISC-V design for FPGA, with SoC & OS, and in a novel HDL|
"A FPGA friendly 32 bit RISC-V CPU implementation" by Charles Pappon
(As it's a RISC-V, there's a GCC already.)
Real time OS:
SpinalHDL is a programming language to describe digital hardware and then generate the corresponding VHDL/Verilog file.
|Author:||BigEd [ Sat Jul 22, 2017 4:44 pm ]|
|Post subject:||Re: A RISC-V design for FPGA, with SoC & OS, and in a novel|
Another open free RISC-V implementation: PULPino.
Via the comments on a Hackaday article on homebrew CPUs.
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