|A dual-ISA RISC - MIPS or RISC-V options
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|Author:||BigEd [ Thu Mar 22, 2018 7:37 am ]|
|Post subject:||A dual-ISA RISC - MIPS or RISC-V options|
This looked interesting:
f32c is a retargetable, scalar, pipelined, 32-bit processor core which can execute subsets of either RISC-V or MIPS instruction sets. It is implemented in parametrized VHDL which permits synthesis with different area / speed tradeoffs, and includes a branch predictor, exception handling control block, and optional direct-mapped caches. The RTL code also includes SoC modules such as a multi-port SDRAM and SRAM controllers, video framebuffers with composite (PAL), HDMI, DVI and VGA outputs with simple 2D acceleration for sprites and windows, floating point vector processor, SPI, UART, PCM audio, GPIO, PWM outputs and a timer, as well as glue logic tailored for numerous popular FPGA development boards from various manufacturers.
An interesting note on size and speed of this RISC vs a 486 SoC:
fastest CPU core I have ever run on my board was F32C (MIPS/RISCV compatible)... At a guess, I estimate that I could possibly fit four such cores, each running @ 100MHz+ on my board and still have room for peripheral or other modules.
From the opensource flea-ohm FPGA board project discussion.
ao486 [runs at 36MHz] is too big to fit inside the ECP5 of my Ohm board AFAICT. From what I've read it is not an optimal x86 solution, but it is the first open and complete 32-bit x86 core for FPGA use.
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