Last visit was: Sat Sep 19, 2020 12:01 am
It is currently Sat Sep 19, 2020 12:01 am



 [ 13 posts ] 
 16/32 bit cpu for a late 1976 cpu. 
Author Message

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
Now that I seem to have got the timing bugs worked on the 18 bit cpu, I will be trying a 8/16/32 bit cpu in TTL with the DE1. 16 bit bus, 1 control and 2 16 bit alu cards. Addressing will be 20 bits with no segments. Register, quick #, R+,-R,R and indexed addresing modes. 8 registers, 32 bits.
About a 1976 time frame, with 512 x 16 bit microcode roms, and ~ .75 us memory cycle.I just have remeber to play a few 8 track tapes when I build this. :)


Mon Jan 06, 2020 7:22 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
Decided to drop this design.I now working on a simple 32 bit cpu, with 32 bit bus and one meg of memory addressing. For now this will be FPGA test project, as I still don't have a good compiler of any kind to write a OS with structures.


Thu Mar 19, 2020 5:11 pm

Joined: Wed Nov 20, 2019 12:56 pm
Posts: 36
oldben wrote:
Decided to drop this design.I now working on a simple 32 bit cpu, with 32 bit bus and one meg of memory addressing. For now this will be FPGA test project, as I still don't have a good compiler of any kind to write a OS with structures.


If you do want to explore getting a compiler up and running for your architecture, I found the VBCC C-compiler's backend interface surprisingly accessible. It's still a lot of work to bring up a new backend, but the fact that you can start with the generic-risc backend and sculpt it to your needs helps a lot.


Fri Mar 20, 2020 6:50 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
Generic RISC ... Ha! This design is old school all the way.
The problem with modern stuff, is they don't fit in 64K of memory with 256K floppies
and that is what I will have on the machine, as this is retocomputing project.
The compiler I have does generate code, just not for 32 bits yet, and I want to add structures
and table constant data. It also tends to lockup with bad input. The Language is a ALGOL
and C cross, integer only at the moment.


Fri Mar 20, 2020 10:19 pm

Joined: Wed Nov 20, 2019 12:56 pm
Posts: 36
oldben wrote:
Generic RISC ... Ha! This design is old school all the way.


In which case, forgive my blasphemy! :D
(Seriously, though, starting with something that already emits code, that you can then iteratively modify is immensely valuable.)

Quote:
The problem with modern stuff, is they don't fit in 64K of memory with 256K floppies
and that is what I will have on the machine, as this is retocomputing project.


Ah, I see your point - realistically you'd want a couple of megabytes for VBCC. (One of my goals for EightThirtyTwo is for it one day to be able to self-host - my target boards have 32 meg, which should be plenty.)

Quote:
The compiler I have does generate code, just not for 32 bits yet, and I want to add structures
and table constant data. It also tends to lockup with bad input. The Language is a ALGOL
and C cross, integer only at the moment.


Sounds interesting - I'm not familiar with ALGOL, but I suspect in the coming weeks I may have plenty of time for background reading!


Fri Mar 20, 2020 11:18 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
I have modified the 20 bit cpu to 32 bit design. I have added the HALT instruction, very useful for debugging. I am going to have to re-think the front panel to match the fact I don't have 32 switches.
I now have to revise software, and am planning a late 1976 design -- 8 inch floppies SD DS ~ 600Kb
and 16K drams. with 64 KB total memory , 24KB space for dos and I/O buffers. Mainframes of that time I guess had 128KB typical memory at the time.


Sun Mar 22, 2020 8:21 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
A major milestone -- I can download and run a blinking lights program. Now If I had a real front panel ... Now to revise the bios, and find a easy file system to boot on the web.


Mon Mar 23, 2020 12:46 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1164
Location: Canada
Sounds good. So this is running in the DE1?

_________________
Robert Finch http://www.finitron.ca


Mon Mar 23, 2020 2:46 am WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
Yes. The coding is AHDL and TTL macros like 74181. I can do prototying with this, so
a real hardware is mostly tested. Of course things are not that simple. But I have lots of time at
home for development, while I wait for fall. Forget get TP, I need printer paper.
I have been looking for other CPU's done for the DE1, but the sites all seem to closed down,
PDP 11 & 6809 (COCO) are out there, but not easy get a downloadble bitstream, that I can upload.


Mon Mar 23, 2020 7:30 am

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
New and improved, now with less magic smoke. Waiting on parts from sparkfun, to fix
the broken SD card interface, I am now planning a new cpu to make 64 bits the default
data size.
Forget RISC, I have BIG IRON COMPUTER , ONE BIC-1. Core memory cycle ~1.2 us.
3 us 8/16/32 bits 4.2 us 64 bits. Still TTL from 1973. Ben.


Thu Jul 23, 2020 2:47 am

Joined: Sat Feb 02, 2013 9:40 am
Posts: 1164
Location: Canada
64-bits has got to be a lot of TTL chips. 16x 74181 ALUs?

_________________
Robert Finch http://www.finitron.ca


Thu Jul 23, 2020 10:59 am WWW

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
The cpu has 32 bit alu, with a 32 wide data bus with core memory cycle timing.
The computer is split into 4 cards: front panel and timing, control logic, 16 bit alu #1
and alu #2. Large 8"x10" cards with 72 pin connectors per card.

Normal data is the 32 bits (low),with a second pass though the alu to sign extend
to for the upper 32 bits. Two memory reads for 64 bit data.

Since this is retro project clock speed and memory is similar to that of 1970's small
computers (pdp/8e) but using LS rather than TTL.
Ben.


Thu Jul 23, 2020 7:06 pm

Joined: Mon Oct 07, 2019 2:41 am
Posts: 130
FPGA timing glitchs has stoped the project.
I need to redesign the cpu timing for a 16 bit cpu, with a 16 bit memory path.
Packing the opcodes make decoding slow,but a 400 ns alu data path looks just
doable with 74xxx and 74Hxx and a 500 ns memory read access time.
Only a simple 32 bit alu is posible.
Ben.


Mon Aug 31, 2020 7:54 pm
 [ 13 posts ] 

Who is online

Users browsing this forum: CCBot and 0 guests


You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot post attachments in this forum

Jump to:  
Powered by phpBB® Forum Software © phpBB Group
Designed by ST Software