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After modifying the soc to use the amba bus, I decided to shelve it and stick with the WISHBONE bus.

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Robert Finch http://www.finitron.ca


Fri Jul 12, 2019 3:08 am
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Thinking that maybe the uart woes are due to the baud generator which used a harmonic synthesizer, the baud generation was switched to use a clock divider. The baud reference clock is 200MHz so some of the higher baud rates are off by a few percent. It also isn’t practical to go beyond 921600 in an FPGA. Having changed the uart to support this I found out it didn’t make a difference. The baud rate was still off by a factor of about 8. Well, I finally checked the input clock to the FPGA and found that the input to the clock generator was set to 100MHz when it should have been 12 MHz. The whole system was running 8.33x too slow. It seems to work now. 6551 compatible uart.

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Robert Finch http://www.finitron.ca


Sat Jul 13, 2019 4:42 am
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Hurrah!

Is the conclusion that WISHBONE is the simplest and best choice for educational use? Good to know.


Sat Jul 13, 2019 8:35 am
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Quote:
Is the conclusion that WISHBONE is the simplest and best choice for educational use? Good to know.

I’m not sure that it would be any better than the AXI bus, but it has fewer signals to it. I coded an AXI version of the soc and there seemed to be about 3x the code for bus interfacing, which maybe isn’t the best if one is trying to read through and understand things. In truth the AXI bus didn’t seem that hard to understand. It might be approachable by looking at one bus at a time because they all operate similarly. Some of the state might seem confusing to someone new though. Having separate read and write address busses with their own valid and ready signals is interesting. The bus is organized to support pipelined burst accesses. But what’s a pipeline again? What’s a burst access?
If building a system with a gui tool it may not matter how complex the bus really is, if it’s abstracted well. But when one starts to look at details…. And try and convince an interested student not to look at details…
WISHBONE has its own set of complexities. It too can support burst accesses. It was designed to be a “free” bus, no license required. It can be simplified to “send out an address and data and wait for an ack back”.
I liked the MOS 65xx/68xx bus for simplicity. “Send out address and data” assume it works. A simple synchronous bus is maybe the easiest to understand.

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Robert Finch http://www.finitron.ca


Sun Jul 14, 2019 3:42 am
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Thanks - good points all! I had a quick look at AMBA and AXI and I begin to see what you mean! Good to see that they are open standards though. Very many years ago we used a valid-hold interface, which seems to be logically the same as AXI's valid-ready, but with a bit of additional cognitive load (hold being not-ready) that turns out to be unnecessary. This was at Inmos, and AFAIR the idea came from a chap who came from Anamartic. I wonder if there's a direct inheritance along the line.


Sun Jul 14, 2019 6:53 am
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Quote:
This was at Inmos, and AFAIR the idea came from a chap who came from Anamartic. I wonder if there's a direct inheritance along the line.
I wonder if the additional cognitive load was due to patents and copyrights. Can a bus be patented / copyrighted? There are only so many sensible ways to implement one.

Spent some time updating the bc6522 code written originally in 2004 to a via6522. Extended the core to operate with 32-bits. The core was desired for gpio interfacing to leds and buttons for CS01. via6522 has an extra timer associated with it (3 timers total) and 32-bit I/O ports.

I downloaded LLVM with the idea of using it as a toolset to compile and assemble riscv programs. I got the most recent release but I don’t see any riscv tools. It'll take me a while to wade through.

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Robert Finch http://www.finitron.ca


Tue Jul 16, 2019 5:09 am
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Got floating-point test vectors from https://www.research.ibm.com/haifa/proj ... eeets.html

I ran a conversion on the test vectors to a format usable by the test benches.
After running the test vectors for the fused-multiply add I have some doubts. Many of the results are the same, but many are not.

Code:
Example:

r-----res----=-----a----*-----b-----+----c-----
0_151dbe9d_6d000000_804aa000_151dbe9d (converted from IBM)
0_ad954000_6d000000_804aa000_151dbe9d (results from test bench)


I hand calculated the above using a calculator and it looks like the results from the test bench are correct, but the result in the converted file isn’t. I’m guessing it’s a glitch in the file conversion.

Code:
Example 2:

0_98000080_cf800000_80000800_81000000   <= test vector
0_0a7ffc00_cf800000_80000800_81000000   <= test bench


The test bench result appears to be correct when hand calculated.

Code:
Example 3:
-Inf * -Nan
0_ff800000_ffffff00_ff800000   <= test vector
0_7fffff00_ffffff00_ff800000   <= test bench


Test bench returns +Nan, test vector shows -Inf.

Code:
Example 4:
-denormal * +Inf
0_7f800000_80000100_7f800000   <= test vector indicates +Inf
0_ff800000_80000100_7f800000   <= test bench indicates -Inf


I expected there would be some cases which were different, but the files are substantially different.

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Wed Jul 17, 2019 3:47 am
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Started working on a small monitor program for CS01. I looked on the web for such a thing and couldn’t find anything. All it has to be able to do is typical monitor commands, dump memory, dump registers, execute code, enter in memory bytes that sort of thing. All I could find were attempts to get LINUX and similar things running on RISCV. It also needs to be written in assembler code as the compiler isn't working yet.

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Robert Finch http://www.finitron.ca


Sat Jul 20, 2019 3:43 am
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Might be worth a look at the monitor program used in the OPC series, written by Dave (hoglet) as a somewhat extended loose port of Bruce Clark's c'mon:
https://github.com/revaldinho/opc/blob/ ... /monitor.s
http://biged.github.io/6502-website-arc ... m/cmon.htm


Sat Jul 20, 2019 6:25 am
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I was able to get a simple dump memory command to work after fixing a bug in the shift instructions.
The shift instructions weren’t picking up the constant shift amount from the instruction register; they were pulling the value from the previous value of the immediate field. This bug manifested itself as improperly output hex bytes.
A bunch more CSR's were added and now the core is up to about 6,600 LUTs. It still fits easily into the smallest Artix-7 A7-15.
The uart6551 core is being used to communicate with a terminal program on the PC. The uart's fifo receive function seems a bit flaky but transmit works okay. For some reason there are extra characters on the receive. So I modified the uart core and allow the fifo's to be disabled. It seems to work better without fifos.

Quote:
Might be worth a look at the monitor program used in the OPC series, written by Dave (hoglet) as a somewhat extended loose port of Bruce Clark's c'mon:
I had a quick look at the code and it looks like I'd be doing a lot to port to the code to riscv. I have several monitors for various processors I was just looking for something canned already.

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Robert Finch http://www.finitron.ca


Sun Jul 21, 2019 4:25 am
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It may be that the OPC monitor isn't a great starting point, but note that OPC7 is a clean regular 32 bit machine, so it might not be so hard. There's a BCPL port too, so that might be applicable.
viewtopic.php?t=480


Sun Jul 21, 2019 12:39 pm
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