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 Nibbler - A Homemade 4-bit CPU 
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Joined: Tue Aug 27, 2013 11:52 pm
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Hi folks, I'd like to call out a new 7400-based custom CPU I'm building. It's a 4 bit CPU called "Nibbler", and more info is on my web site here: http://www.bigmessowires.com/category/nibbler/

My goals are to keep the chip count to an absolute minimum, while still being able to run some interesting programs like Simon or Mastermind or Hammurabi. Everything is common 7400-series parts except the RAM and ROM, and the plans call for just 16 chips, which is very lightweight compared to past custom CPUs I've built.

I've posted some schematics and design notes to my site, and I'd welcome your feedback. Thanks!


Tue Aug 27, 2013 11:55 pm
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Nice to have you signed up!

(BMOW and I have had some conversation on wire-wrap behind the scenes.)

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Wed Aug 28, 2013 12:33 am
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Good stuff, Steve! thanks for posting. I've only just begun looking at this project, but I can see it's got all the right ingredients for a good time!

One suggestion for the doc: would it make sense to post a diagram showing the instruction format? Lotsa folks (I'm one) feel more comfortable with a picture to help frame the concept.

on your site you wrote:
With two chips that are only half-used, is there a way to combine the functions of the ’173 and the ’175 into a single chip? Probably not: flip-flops load data on every clock, but the ’173 needs a load enable for the ALU flags.

The 74_298 might satisfy this need. It's a 4-bit-wide, edge-triggered register, and there are 2:1 mux's that feed the D inputs.

Bitwise fashion, you can choose the behavior you need. [Edit: see diagram in my subsequent post]

For the bits you want to imitate a '173 (and its conditional loading of new data), tie one of the '298 mux inputs to your source and the other to the '298's own Q output (to recirculate the existing data). The mux Select input becomes "load enable." For the bits you want to imitate a '175 (and its UN-conditional loading of new data), tie both mux inputs to your source.

A coupla possible down sides: the clock is negative-edge triggered, which perhaps isn't convenient. And, although I haven't checked, I doubt you'll find this chip implemented in CMOS (HC/HCT). Would a 74LS298 be acceptable?

on the run... cheers, bye for now :P

Jeff
http://LaughtonElectronics.com


ps- FWIW, IIRC the '398 is a 20-pin version of the '298. It features complementary (Q and /Q) outputs.

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Last edited by Dr Jefyll on Thu Aug 29, 2013 4:22 pm, edited 1 time in total.



Wed Aug 28, 2013 4:56 pm
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Thanks Jeff! I'll be posting more on the instruction format and instruction set details soon -- hopefully tomorrow.

The '298 is a fascinating part I was totally unaware of, so thanks for the pointer! It looks like there's actually some 74HC298s available on eBay too. Offhand I'm not sure how I'd use it to combine the two chips I mentioned, though. I think what I need is something like a 175 that also has a load enable (or clock enable) for each input. The '298 is like a '175 with the ability to choose which source it loads from, but it doesn't have a load enable.

Actually scratch that - I think this could be done with the '398, but it would be a little bit confusing to look at. You could put Phase on Qa, and connect /Qa to both I1a and I2a. Also put /Reset on Qb, and connect the reset capacitor (RC in my diagram) to both I1b and I2b. That way these two signals would always be loaded with the same value regardless of the state of the select input, just as with the '175. Then put Carry on Q1c and I2c, and Equal on Q1d and I2d, finally connect the ALU carry output to I1c and equal output to I1d. That way the flags will be loaded with their existing value when the select input is 1, or with the ALU outputs when the select input is 0, so the select input would function like a load enable for these signals.

I'm all about reducing the chip count for this project, as keeping things simple has been my primary goal. But I'm not sure if this would be a good improvement. Although it would reduce chip count, it would require some extra explanation for anyone studying the CPU, and is not initially obvious why it works. So I'm leaning towards keeping the design as-is, but I'll give it some more thought.

Thanks again!


Thu Aug 29, 2013 12:22 am
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bigmessowires wrote:
Although it would reduce chip count, it would require some extra explanation for anyone studying the CPU.
Fair enough -- that's your call to make. It boils down to a choice, doesn't it: extra explanation, or extra wiring (for an additional IC). :) FWIW, I like how the mux thing illuminates what a '173 (or '377) does internally. The load vs recirculate model is something worth learning -- a mainstay of MSI as well as programmable logic.
Attachment:
'173 and '174 in one package.gif
'173 and '174 in one package.gif [ 5.61 KiB | Viewed 8986 times ]
Here's a diagram, in case anyone got snowed under by our verbiage! Steve, I guess if you used a '398 then the complementary outputs would come in handy. But this diagram is general, not specific to Nibbler.

cheers,
Jeff

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Last edited by Dr Jefyll on Fri Sep 13, 2013 9:13 pm, edited 3 times in total.



Thu Aug 29, 2013 7:47 am
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Nice diagram! What software did you use to draw it?

Yes, in my case I would need a '398 with the complementary outputs, rather than a '298, because the Phase signal is supposed to constantly toggle from 0 to 1 and back.


Thu Aug 29, 2013 2:08 pm
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There are a few other places where I was surprised I couldn't find the 7400 part I wanted. In particular, there doesn't seem to be any 8 bit counter that can be loaded with an arbitrary value. The '393 is an 8 bit counter (actually dual 4 bit) that counts from 0, the '163 is a 4 bit counter that can be initialized to any value you'd like. I need something like an 8 bit version of the '163.

Another one that would be handy but doesn't seem to exist is a dual '173. This would be a dual 4-bit register with a load enable input for each nibble. The closest is the '377, but it has only a single load enable input for the whole byte.


Thu Aug 29, 2013 2:21 pm
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bigmessowires wrote:
Nice diagram! What software did you use to draw it?
I use Paint Shop Pro, a high-end image editor roughly equivalent to Photoshop. Programs like that don't "understand" schematics -- there are no CAD smarts. So the downside is, you have to do everything yourself. But that's also the upside! :D You're free to tell the story in whatever way best puts the point across.

Quote:
The '298 is a fascinating part I was totally unaware of
Yeah, it's a handy little beastie, fer sure! In this project I used a pair of them to create a load/shift register for video. (Schematic excerpt below.)
Attachment:
load-shift register using '298s.gif
load-shift register using '298s.gif [ 2.64 KiB | Viewed 8986 times ]

Also speaking of 298's, the old Diablo daisywheel printers had a custom CPU built out of MSI, and it included two pairs of '298's for the Operand A and Operand B registers. There's a bit of a writeup on my web site here, and the complete schematic of this minimalist CPU is here.
Quote:
I need something like an 8 bit version of the '163. [...] Another one that would be handy but doesn't seem to exist is a dual '173.
Yes, over the years I've often wished for an 8 bit version of the '163. But there aren't a lot of new MSI building blocks being introduced lately, thanks to the awesome programmable logic we have nowadays.

As for a dual '173, maybe you could kludge a 74ALS874 to fit the bill. It has two independent sections, each of which is a 4-bit, edge-triggered register. Unfortunately, the data enable feature is missing. Nevertheless, you still have the (somewhat inelegant and potentially problematic) option of gating the clock signal fed to the device. :?

cheers,
Jeff

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Last edited by Dr Jefyll on Fri Sep 13, 2013 9:16 pm, edited 1 time in total.



Thu Aug 29, 2013 4:11 pm
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I'm impressed you drew those diagrams by hand with a paint program. You must have a lot more patience than I do! :-)

I posted some more info on the instruction set that hopefully makes things clearer. Thanks again for your advice.


Fri Aug 30, 2013 12:55 am
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bigmessowires wrote:
I posted some more info on the instruction set that hopefully makes things clearer.
Excellent. I find a diagram showing the instruction format to be essential when getting acquainted with an unfamiliar CPU. Now I'm starting to feel I have a grasp of what's going on!

There were a few, "Oh, now I get it moments." For me, it would've been helpful if (in addition to the instruction formats) certain key details were revealed immediately, preferably in the introduction. For example (not necessarily a complete list)...
  • the ALU is 4 bit
  • the data space is organized as 4 bit words, selected by a 12 bit address
  • the code space is organized as 8 bit words, selected by a 12 bit address
  • the microcode ROM array is organized as 16 bit words, selected by a 7 bit address
  • every instruction entails two fetches from the microcode ROM array

bigmessowires wrote:
I'm impressed you drew those diagrams by hand with a paint program. You must have a lot more patience than I do! :-)
I don't find that it taxes my patience; it's actually kinda fun. And of course with practice you become more & more proficient.

FWIW, here's another diagram, this one a rework of one of your own. To me this is more clear than the original, mainly because the signal flow is more linear and is predominantly from top to bottom. As with my other suggestions, I offer this respectfully, realizing that my way of learning and thinking may differ from others'.

-- Jeff
Attachment:
nibbler_arch rev1 jwl.png
nibbler_arch rev1 jwl.png [ 34.98 KiB | Viewed 8986 times ]

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Last edited by Dr Jefyll on Fri Sep 13, 2013 9:20 pm, edited 1 time in total.



Fri Aug 30, 2013 4:55 pm
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Thanks Jeff. OK if I repost your diagram to my blog?

By the way, I must have a very poor memory for making that comment about Paintshop Pro, since I drew the architecture diagram with The Gimp. :-)

I think I did mention all your "now I get it" points in the introductory post on my blog, but they were in narrative form, or implied by the diagram. Thanks for calling those out specifically.


Fri Aug 30, 2013 11:25 pm
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bigmessowires wrote:
By the way, I must have a very poor memory for making that comment about Paintshop Pro, since I drew the architecture diagram with The Gimp. :-)
Hah! I wondered about that! :D And yes, of course you may repost the drawing... although there are some ICs that remain unlabeled. That and any other tweaks I leave up to you.

Quote:
I think I did mention all your "now I get it" points in the introductory post on my blog, but they were in narrative form, or implied by the diagram.
True. But I think there's a lot to be learned from the style of presentation found in commercial microprocessor Data Sheets. There, you'll notice the introduction typically makes use of a few diagrams and some bulleted points that establish the basic premise of the product. After that, narrative can be used to amplify and discuss the details.

The embarrassing truth is that I can be a lazy reader at times, and tend to skip tracts of narrative unless they're short. This behavior is typical of a lot of people! That's why writers of good doc make the initial description as easy to digest as possible.

Not that it's easy to write good doc -- I've tried, and know it isn't!!! Also, I realize you're writing a blog, not a Data Sheet per se.

-- Jeff

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Sat Aug 31, 2013 1:05 am
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Here's another take on arranging a flipflop so there's Data Enable capability on some bits but not others. Note: CMOS logic strongly recommended! This approach is decidedly dicey for 74LS and other TTL families.
Attachment:
'174 with ersatz Mux.gif
'174 with ersatz Mux.gif [ 8.36 KiB | Viewed 8986 times ]
The idea is the same as in my earlier post and diagram with the '298. However, in this version the Mux effect is created using a tri-state buffer and some resistors. 1K0 is a guesstimate; you may want a lower resistor value if speed is an issue (less RC delay), or a higher value if you'd prefer to save power (less dissipation on the resistors). Check the spec's for the logic family/families in question (4000, 74HC, 74AC series etc). The minimum acceptable resistor value is determined by the output drive capability of the 367 and of the flipflop (during the times they're fighting each other across the load created by the resistors) and the input voltage requirements of both the flipflop and whatever downstream circuitry is attached. That's assuming said circuitry presents no appreciable DC loading (ie, more CMOS). You need to run some numbers if you want guaranteed results with this. The numbers should be easily satisfied as long as speed and power issues aren't critical. For a one-off project you may prefer a seat-of-the-pants approach. (Just build it, 'scope it, then tweak the resistor and see how fast the thing will run.)

Steve, you'll like the fact that the 74HC367 has two sections. The 4-bit section can replace the '125 in your original plan, so in that sense the 2-bit section is "free." :D

ETA: Or, swap out the '125 for a 74HC268, the inverting sibling of the '367. As a side effect your input data will read inverted, and that's probably tolerable. Balancing that, you get to increase your gate budget to the tune of two inverters. :ugeek: (Just ground /OE for that section.) Alternatively, swapping a '240 for the '125 would yield four extra inverters.

-- Jeff

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Tue Sep 03, 2013 7:57 pm
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