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 LALU Computer: Lookup Arithmetic Logic Unit 
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Joined: Wed Jan 09, 2013 6:54 pm
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Yeah, give yourself a clean power supply - the alternative is to be chasing down rare glitches. Decoupling caps are there to keep the very local power clean.


Fri Dec 30, 2022 9:16 am
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Location: Michigan USA
As mentioned previously I am attempting to increase the clock speed on LALU from 1 MHZ to 4 MHZ. At the moment I am at about 99% there, but have spent the last 2 days trying to track down erratic results. It was especially aggravating because I could not get back to normal operation at 1 MHZ. (You know that feeling when you try to get back to the 'good' operating condition you consider as a baseline.)

Well, the whole thing was driving me nuts! Finally, I recalled an old saying about sometimes what is wrong with electrical PCBs is often obvious to the eye. I pulled every PCB in LALU and inspected every solder joint... and what do you suppose I found? Two connections that were not soldered! They must have been making contact originally, and then when I started pulling and swapping boards the issues started to show up. Ha!


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Sun Jan 01, 2023 10:21 pm
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Nice project! Your block diagram looks quite similar to mine - including the PC being updated via the address bus, so I guess like me you can't read the PC's value which would be nice for subroutine calls.

My ALU is two 64KB EEPROMs, each working on four bits in a ripple carry configuration. So I don't have MUL or DIV, but I did manage to implement ROR in two cycles which is useful for multiplication.

How fast do you think your system can go - have you looked at how long the critical path is? Bearing in mind things are often faster than claimed - my 45 ns EEPROMs only take about 20-25 ns in practice.

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-Kyle
dip16.com


Fri Jan 06, 2023 5:46 pm
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Hi, When I first started the LALU project I was using a buffered toggle switch for the clock. From there I added a 555 timer circuit, and I used the 555 for awhile running at about 50 HZ. After that I bumped it up to 1 MHZ for about the last 6 months. Lately I have been attempting to increase the speed, and it's an active project. I have things working well at 1.8 MHZ, but I see a few glitches on the oscilloscope due to timing issues... so I am focused on fixing those right now. I did try running at 4 MHZ but found some of the operations were intermittent. Maybe after I fix the glitches.

Also, I forgot to mention previously that I uploaded zip files with schematics, gerbers and development software on my website (near the bottom). It's all a work in progress.

http://www.mtmscientific.com/lalu.html


Tue Jan 10, 2023 8:00 pm
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Here's a quick update on the LALU computer and the Threaded Interpretive Language for it called LANG.

I spent quite of bit of time experimenting with clock speeds. Operation at 4 MHZ is intermittent, but I did manage to run the benchmark Prime Number Sieve program in 14 seconds. That compares to my very first run of the program at 360 seconds, many, many changes ago. I am going to stick with a 1 MHZ crystal oscillator, as I just like the round number-rock solid feel of it.

A primitive line editor capability has been added to LANG. Each line of LANG text code going to the parser is held in a hardware stack. Presently I have 16 stacks for that purpose (16 lines of code), and I am considering increasing that to 256.

I've spent alot of time thinking about boot strapping a higher level language for LALU. I seem to have gravitated to EFORTH or Small-C. In that regard I want to say how much terrific information and links have been collected on this website! Thank You. It makes exploring options fun.

My I/O hardware on LALU needs improvement. I am designing a new I/O board to include parallel I/O using an 8255A PIO. I'm also toying with the idea of doing RS-232 bit banging, or adding a serial I/O chip from the TTL family. It would be fun to hook up a VT-100 serial terminal or similar, but apparently those have gone from being free for the taking to collectibles. Ha!

Michael


Mon Jan 30, 2023 10:31 am
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Here are a few diagrams and photos explaining the operation of the Keyboard Stacks in the LALU computer. The Stacks in LALU are hardware stacks. The Keyboard Stack has 6 assembly instructions for control. They are: Zero the Stack Pointer, Decrement the Stack Pointer, Increment the Stack Pointer, Read the Stack Cell, Write the Stack Cell and Jump to another Keyboard Stack.

The Keyboard Stacks are used to hold ASCII character bytes that represent the individual characters of programs written in LANG. These characters are read by the Parser. The Parser can be thought to be more akin to the NEXT engine. A simple 3 line program to continuously print "HI" on the LCD Display is shown.

When the Parser sees the ASCII symbol for quotation mark the Parser/Next Engine jumps to memory segment Hx022 (ASCII value for ") where there is an assembly routine to keep writing characters to the LCD until another quotation mark is found.

When the Parser sees the ASCII symbol for "S" it jumps to memory segment Hx53 and runs a delay loop. When the Parser sees the ASCII symbol for "G" in the next line it jumps to a routine that does a Keyboard Stack Jump.


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Fri Feb 03, 2023 2:41 pm
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Hi, Just a quick update on the LALU computer. I've added a Parallel I/O capability using a P8255A-5 IC. For the address decoding I am using 74LS085 chips. The I/O is memory mapped to the top of my 64K address space starting at FF:F0. I added a small area to do some breadboarding for the I/O as shown in the attached photo.

Adding a parallel port was surprisingly easy to do, so I am proceeding with the addition of Serial I/O using the P8251A. The ability to send and receive a serial character is a basic requirement for some of the languages I have examined for bootstrapping.

I also continue to make improvements to my computer language LANG. I have a primitive editor working, and can load files from ROM memory for execution. LANG has two execution modes: Immediate Mode and List Mode. Eventually I would like to have the editor work with files using serial I/O. At the moment I can only input files using the keyboard or burning into ROM.


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Tue Feb 14, 2023 12:42 pm
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mmruzek wrote:
Hi, Just a quick update on the LALU computer. I've added a Parallel I/O capability using a P8255A-5 IC. For the address decoding I am using 74LS085 chips. The I/O is memory mapped to the top of my 64K address space starting at FF:F0. I added a small area to do some breadboarding for the I/O as shown in the attached photo.
.

This reminds of all the projects that added a IDE drive interface for a z80. using a 8255. You might want to reserve I/O space for
that. Ben.
PS.How do you get them PCB's looking so good?


Tue Feb 14, 2023 8:30 pm
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Connecting an IDE hard drive to a homebrew computer using the 8255 Parallel I/O chip is an interesting idea! Doing a little searching I found a very useful webpage on that topic here:

https://www.pjrc.com/tech/8051/ide/

The interface wiring actually looks pretty easy... the heavy lifting apparently is the coding. I've attached a wiring schematic from the referenced webpage that makes it look deceptively simple.

Regards my PCB layouts the biggest items in my learning curve were to embrace vias, and to systematically use a horizontal/vertical stategy for the top and bottom layers. Another practice I have found helpful is to use the silkscreen layer to add labels on lines and important pins. The labels make it easier for me to remember what I was doing when I go back to look at a board. A great convenience for layout has been creating an 8 line data bus that runs under the 0.600" wide ICs and connecting to the pins using vias. I am not suggesting this is a best practice! I am only running at 1 MHZ so things are very forgiving and I get away with it OK.


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Wed Feb 15, 2023 12:43 pm
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Just a quick update on the LALU computer project... I have the serial port communication using an 8251 USART working and transferring files back and forth to a laptop asynchronously.

One major update has been to the Oscillator / Ring Counter board. Previously I had allowed for 6 rings, with the first ring always being an instruction fetch. It turns out I was not using the last 2 rings for any of the hardware operations so I eliminated them. The net result was making LALU 33% faster while still running at 1 MHZ.

I decided to run another benchmark, this time the calculation of the first 25 Fibonacci numbers. Here are a few links to a discussion here and elsewhere about the benchmark:

https://hackaday.io/project/167605-kobo ... ing-anyway

viewtopic.php?f=8&t=447&p=5797&hilit=Fibonacci+benchmark#p5797

Generally it looks like this calculation is repeated 10 times for comparison. I wrote the program to do the calculation in my interpreted language "LANG" and did the calculation 100 times in 7 seconds, which then would be 0.7 seconds for 10 runs.

Michael


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Wed Mar 08, 2023 3:48 pm
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I am thinking lately of hybrid F+7 arithmetic with 8 bit logic. Makes for very cramped 128byte pages...
F+15, or Flag+Sign+14 make better pages, but unreasonable arithmetic and multiplication tables.

Arithmetic and logic don't worry so much, cause I got an easy series prefix ALU already wired.
Most every primitive double argument is already hardwired and not much in need of lookup.
But multiplication and division are not within it's capabilities, except the long way bitwise.

A*B High and Low byte tables of 64K each, can only multiply 8bit arguments in two lookups.
Still a few long multiplication steps to assemble larger arguments.

I read somewhere of a procedure to multiply using only a one-argument lookup, twice.
A*B=(((A+B)^2)/4)-(((A-B)^2)/4), only requiring a manageable size table of N^2/4.
Is some similar trick available for division?


Mon Mar 20, 2023 9:06 pm
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I think speeding up division is really hard!


Mon Mar 20, 2023 9:24 pm
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On the LALU computer I still have not brute-force coded the assembly for multiplication and division operators, hoping that something better might come along suited to using Lookup Tables. One thing that looks interesting is the Quarter Square Multiplication Tables. Apparently these have a historical basis. Here are a few links (Scroll down on the Wiki link to relevant heading. It's a good read) :

https://forums.atariage.com/topic/23684 ... ultiplies/

https://en.wikipedia.org/wiki/Multiplic ... iplication

For the division operator I would like to make available both the quotient and remainder from the operation by default.


Mon Mar 20, 2023 9:38 pm
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For fast division, maybe start with wikipedia
https://en.wikipedia.org/wiki/Division_ ... on_methods


Mon Mar 20, 2023 9:42 pm
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Some time back I was experimenting with fast(er) multiplication for the 6502/65816 and there were others in the 6502org forum who contributed, but at one point, as I had a 65816 with 512KB of RAM, I populated 2 x 64K banks with the 16-bit results of all 8x8 multiplies (unsigned) then it was a fairly trivial bit of code to use that in a sort of shift & add sort of way to do multi-byte arithmetic. (easy since the shifts were 8 bits).

It was very fast. No loops, and using the index registers made it relatively trivial to do the table lookups.

I'd have kept it in if I had more RAM in the system, but that 128KB out of the 512KB total did make it impossible to run the BCPL compiler.

But if you have 128KB "spare" ...

-Gordon


Mon Mar 20, 2023 9:56 pm
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