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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2095 Location: Canada
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I found some old schematics for this project that I mentioned in another thread. I took the time to redraw them in a CAD program many years ago, before 1999. A bit of nostalgia. There may be a schematic missing; I thought there were five but I could only find four. ALU Attachment:
File comment: ALU for b16 CPU
alu.gif [ 151.11 KiB | Viewed 6135 times ]
EXEC Attachment:
File comment: EXEC logic for b16 CPU
exec.gif [ 87.81 KiB | Viewed 6135 times ]
OPFETCH - Opcode Fetch Attachment:
File comment: Opfetch logic for b16 CPU
Opfetch.gif [ 20.14 KiB | Viewed 6135 times ]
SR - Status Register Attachment:
File comment: SR for b16 CPU
sr.gif [ 32.47 KiB | Viewed 6135 times ]
_________________Robert Finch http://www.finitron.ca
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Tue Jan 10, 2023 4:16 pm |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2095 Location: Canada
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Some more info
Address Modes Implemented in Minimal Processor opmode reg mneumonic description 000 rrr r ; register direct 001 rrr [r] ; register indirect 010 rrr [--r] ; register indirect pre decrement 011 rrr [r++] ; register indirect post increment 011 111 # ; immediate
Register Summary
Programmers Registers
bit pat. mneumonic rrr 000 r0 001 r1 010 r2 011 r3 100 r4 101 fp frame pointer 110 sp stack pointer 111 ip instruction pointer
sr status (flag) register
status register bits 54321098 76543210 xxTxIIII xxxxNVZC-carry | |||| ||+--zero | |||| |+---overflow | |||| +----negative | ++++----------interrupt level +---------------trace
Opcode Formats --------------- Dual operand oooo sss SSS ddd DDD Single operand 0000 oooo xx ddd DDD Program control 0001 cccc xx ddd DDD
oooo - opcode cccc - condition sss - source addressing mode ddd - destination addressing mode SSS - source register DDD - destination register xx - don't care (reserved)
Dual operand instructions oooo sss SSS ddd DDD oooo 0000 { single operand/ miscellaneous } 0001 { flow control } 0010 add 0011 addc 0100 sub 0101 subb 0110 cmp 0111 cmpb 1000 and 1001 or 1010 xor 1011 { set cccc } (maximal) 1100 1101 move 1110 test 1111 reserved
Single Operand Instructions ----------------------------
Shift/Rotate 0000 0ooo xx ddd DDD
ooo ||+- |+-- 0 = normal, 1 = circular +--- 0 = shift left, 1 = shift right
000 { miscellaneous instructions } 001 lsl,asl - arithmetic shift left or logical shift left 010 rol - circular shift (rotate) left 011 rolc - circular shift left through carry 100 asr - arithmetic shift right 101 lsr - logical shift right 110 ror - circular shift (rotate) right 111 rorc - circular shift right through carry
Negate/Increment/Decrement/Clear 0000 1ooo xx ddd DDD
ooo
000 not - ones complement 001 neg - twos complement (unimplemented) 010 inc 011 dec 100 clr 101 pea - push effective address (maximal) 110 111
0001 cccc xx ddd DDD
Program Control Instructions ------------------------------------------------ cccc flag combination 0000 cs/lo c 0001 cc/hs !c ; these are simple tests based on individual 0010 vs v 0011 vc !v ; condition code bits being set or clear 0100 eq/z z 0101 ne/nz !z 0110 mi n 0111 pl !n
1000 to 1111 0 ; always false
_________________Robert Finch http://www.finitron.ca
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Tue Jan 10, 2023 4:34 pm |
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mmruzek
Joined: Sun Dec 19, 2021 1:36 pm Posts: 74 Location: Michigan USA
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Hi, Thanks for posting these schematics. Do you recall what was done for clocking...? It might be there somewhere, but I'm not seeing it. Also, do you have a photo of the project? Thanks! Michael
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Tue Jan 10, 2023 7:43 pm |
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DockLazy
Joined: Sun Mar 27, 2022 12:11 am Posts: 40
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It's really nice to see a hobby computer using SRAM for a register file. And hardware instruction decoding.
Took me a while to figure out why the carry out from the ALU was so busy, rotate instructions, duh. Also I've thought about using that trick of using an extra 181 to generate an overflow flag via a guard bit. If I recall correctly the extra XOR gate wasn't needed*.
*I remember now why the XOR wasn't needed, I was detecting signed carry not actual overflow.
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Tue Jan 10, 2023 10:45 pm |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2095 Location: Canada
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Quote: Do you recall what was done for clocking...? It might be there somewhere, but I'm not seeing it. Also, do you have a photo of the project? Thanks! Michael No photo of the project. It never made it off the drawing board. The clock may have been on another schematic which I cannot find. I believe the clock was single phase canned oscillator possibly with a divider. There is a note on the schematic that all FF's are 74ls273's with a common clock and reset. There is a signal labelled 'CLK' which feeds a chip or two. Most of the synchronous logic uses the '273 ff. I have a bunch of '273s I collected for the project but did not end up using. Quote: Took me a while to figure out why the carry out from the ALU was so busy, rotate instructions, duh. Also I've thought about using that trick of using an extra 181 to generate an overflow flag via a guard bit. If I recall correctly the extra XOR gate wasn't needed*. I wish the '181 had an overflow output, and a zero result output. Overflow can be calculated looking at the opcode, and high order bits of operands and the result. But it is a few more chips.
_________________Robert Finch http://www.finitron.ca
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Wed Jan 11, 2023 12:05 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am Posts: 594
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The 74181 seems to better designed for negative logic. I remember having a design where I used 3 bits of data, for the 4 bit alu chip Bit #4 input was always set to 0,1 so carry out would be correct. This had 2 9 bit alu cards.
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Wed Jan 11, 2023 7:31 pm |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2095 Location: Canada
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Quote: The 74181 seems to better designed for negative logic. I think it was designed to go along with buffers / multiplexors that used inverting logic to improve performance. Quote: I remember having a design where I used 3 bits of data, for the 4 bit alu chip Bit #4 input was always set to 0,1 so carry out would be correct. This had 2 9 bit alu cards. But the '181 has ripple carry input and output. Was it faster to use the input bit? Quote: This had 2 9 bit alu cards. 18 bit CPU?
_________________Robert Finch http://www.finitron.ca
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Thu Jan 12, 2023 12:17 am |
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oldben
Joined: Mon Oct 07, 2019 2:41 am Posts: 594
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robfinch wrote: I think it was designed to go along with buffers / multiplexors that used inverting logic to improve performance. 18 bit CPU? It was a a expanded 6800 like cpu, with a PC,AC,SP,IX. I never could get a instruction set I liked to fit into a 9 bit opcode.
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Thu Jan 12, 2023 4:00 pm |
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robfinch
Joined: Sat Feb 02, 2013 9:40 am Posts: 2095 Location: Canada
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Thinking of implementing something similar to the b16, but using higher scale integration. As a result of drooling over am2901 chips but not really wanting to assemble a system using real chips, I created a Verilog code version of the am2901 with a couple of twists. More registers, up to 64, and better I/O for use in an FPGA. It also supports 3R access, 2 source 1 target, to the register file instead of 2R. Also worked on a 12-bit version of the am29112 microprogram sequencer but it is not completely coded yet. Quote: It was a a expanded 6800 like cpu, with a PC,AC,SP,IX. I never could get a instruction set I liked to fit into a 9 bit opcode. Needs a second index register. Handy when copying source to destination. 6800 has two accumulators too.
_________________Robert Finch http://www.finitron.ca
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Sat Jan 14, 2023 4:45 am |
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