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 My I/O Questions 
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Joined: Sat Aug 03, 2013 11:02 pm
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To keep from getting too many questions, I will put majority of my I/O questions in here. To start: This Decoder
http://sbc.rictor.org/decoder.html. Are there other chips like it, specoficly for the 6800 or the 8080. I do plan to use it in a 6502 project (I hate decoding myself), but I want to know if i could have other uses, or if there is antoher chip that can do the same thing for the two other mpu's listed

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Fri Oct 25, 2013 12:03 pm
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James_Parsons:

The decoder to which you refer is based on a programmable device variously known as a GAL (Generic Array Logic), PAL (Programmable Array Logic), or CPLD (Complex Programmable Logic Device). The device shown in Daryl's schematic is referred to as a GAL22V10 device. (Note: I don't consider there to be any significant differences between PALs and GALs. They are simply trade names for programmable logic devices from different manufacturers with essentially the same functions/capabilities.)

The generally accepted part numbering convention used for most PAL/GAL devices is to define the total number of inputs into the array, followed by a letter, followed by the number of outputs. In the case of Daryl's decoder, there are 22 general purpose inputs into the array. Both the non-inverted and the inverted versions of these signals (logic array inputs) are available for use. Thus, there are generally 44 signals that can be used as inputs to the logic equations. The letter is a "V" which signifies that the 10 outputs may be used as registers, inputs, bidirectional or tri-state signals, or combinatorial outputs. Other commonly used letters are "L", "C", and "R". An example device using these other letters are the 16L8 and the 16R4 PALs. The 16L8 device indicates that there are 8 active-low combinatorial outputs, which are fed back into the array. The 16R4 has a total of 16 signals into the logic array consisting of 12 general inputs, and 4 registered outputs. Finally, most PAL/GAL devices provide at least one tri-state output control signal. It may be dedicated, i.e. not plugged into the logic array, or it can be controlled from the logic array.

For a 6800 microprocessor, I think that you could adapt Daryl's decoder as is. An 8080 microprocessor, on the other hand, has a separate 8-bit address space for I/O devices. It expects that user I/O uses its two dedicated instructions for accessing I/O. Both MOS and Motorola adopted a memory-mapped I/O concept, but Intel/Zilog/AMD devices use the concept of separate memory (for instructions and data) and I/O. Special instructions are used to read (IN) and write (OUT) the registers of I/O devices.

Memory-mapped is considered by some to be dangerous, but others find that the memory-mapped I/O concept allows full (or almost full) use of the addressing modes of the microprocessor for directly manipulating the I/O registers. However, there are some issues with that.

For example, most CISC microprocessors which implement memory-mapped I/O, also support some pretty sophisticated Read/Modify/Write addressing modes. These RMW instructions can play havoc with some common I/O devices structures such as the receive and transmit FIFOs of a UART. In many of these devices, to save pins, the designers implemented the receive and transmit FIFOs such that they share a single address. The read/write control signals of the processor determine whether one or the other of these two FIFOs is accessed. If you inadvertently apply such an instruction to the address representing (decoding to) the receive FIFO and simultaneously to the transmit FIFO, the receive data would be read from the receive FIFO, modified by the instruction, and written to the transmit FIFO. In general, this is not likely the desired operation. However, this may be what is desired. So the RMW instruction applied to the the address of the receive/transmit FIFOs transforms the receive data and transmits the modified data in a single instruction cycle.

The Intel architectures support a separate address space for I/O devices. The claim is that the situation described above can't occur in a microprocessor with separate I/O and memory spaces. In most cases that is true, but as you can imagine, being able to apply a data transformation in a single cycle using memory-mapped I/O is very likely to be faster that the same transformation using IN and OUT instructions. On the other hand, not giving up memory address space to I/O devices may be just as important. Finally, there's no reason why an Intel microprocessor cannot use memory-mapped I/O.

Thus, if you'll contact Daryl by PM, you may be able to buy a pre-programmed decoder device from him, or he may point you to any open source files of programming for the device.

(Edit: corrected some grammatical errors as pointed out by Garth.)

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Last edited by MichaelM on Fri Oct 25, 2013 10:29 pm, edited 1 time in total.



Fri Oct 25, 2013 9:05 pm
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Quote:
known as a GAL (Generis Array Logic)

Did you mean Generic Array Logic?

I have often used RMW instructions with the 65c22 in particular to quickly change one bit at a time; so I'm glad for the possibility. With the 65816's 16-bit operations, memory-mapped I/O also lets you read or write both 8-bit ports at once, or both their data-direction registers at once.

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Fri Oct 25, 2013 9:47 pm
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Another one on the DEC-1 chip. It supports 4 I/O devices. Does this mean i can have 4 VIA's with 2 ports on each, or 2 VIA's with2 ports one each
Also will this memory map support ehBASIC
May i use http://sbc.rictor.org/vid3.html and possibly http://sbc.rictor.org/pckb6522.html in my 6502 system

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Mon Oct 28, 2013 12:01 pm
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The four devices would mean four I/O ICs with everything that's on each. So yes, you could have four VIAs, or three VIAs and an ACIA, etc.. Four VIAs would mean 80 I/O bits if you include CA1, CA2, CB1, and CB2 on each. The things of Daryl's that you linked to can be connected to one of your VIAs, still leaving lots of other I/O available. I have not used EhBASIC but from all I've read, it is apparently very easy to adapt to different memory maps and I/O types.

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Mon Oct 28, 2013 8:27 pm
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MichaelM wrote:
James_Parsons:

The decoder to which you refer is based on a programmable device variously known as a GAL (Generic Array Logic), PAL (Programmable Array Logic), or CPLD (Complex Programmable Logic Device). The device shown in Daryl's schematic is referred to as a GAL22V10 device. (Note: I don't consider there to be any significant differences between PALs and GALs. They are simply trade names for programmable logic devices from different manufacturers with essentially the same functions/capabilities.)

The generally accepted part numbering convention used for most PAL/GAL devices is to define the total number of inputs into the array, followed by a letter, followed by the number of outputs. In the case of Daryl's decoder, there are 22 general purpose inputs into the array. Both the non-inverted and the inverted versions of these signals (logic array inputs) are available for use. Thus, there are generally 44 signals that can be used as inputs to the logic equations. The letter is a "V" which signifies that the 10 outputs may be used as registers, inputs, bidirectional or tri-state signals, or combinatorial outputs. Other commonly used letters are "L", "C", and "R". An example device using these other letters are the 16L8 and the 16R4 PALs. The 16L8 device indicates that there are 8 active-low combinatorial outputs, which are fed back into the array. The 16R4 has a total of 16 signals into the logic array consisting of 12 general inputs, and 4 registered outputs. Finally, most PAL/GAL devices provide at least one tri-state output control signal. It may be dedicated, i.e. not plugged into the logic array, or it can be controlled from the logic array.

For a 6800 microprocessor, I think that you could adapt Daryl's decoder as is. An 8080 microprocessor, on the other hand, has a separate 8-bit address space for I/O devices. It expects that user I/O uses its two dedicated instructions for accessing I/O. Both MOS and Motorola adopted a memory-mapped I/O concept, but Intel/Zilog/AMD devices use the concept of separate memory (for instructions and data) and I/O. Special instructions are used to read (IN) and write (OUT) the registers of I/O devices.

Memory-mapped is considered by some to be dangerous, but others find that the memory-mapped I/O concept allows full (or almost full) use of the addressing modes of the microprocessor for directly manipulating the I/O registers. However, there are some issues with that.

For example, most CISC microprocessors which implement memory-mapped I/O, also support some pretty sophisticated Read/Modify/Write addressing modes. These RMW instructions can play havoc with some common I/O devices structures such as the receive and transmit FIFOs of a UART. In many of these devices, to save pins, the designers implemented the receive and transmit FIFOs such that they share a single address. The read/write control signals of the processor determine whether one or the other of these two FIFOs is accessed. If you inadvertently apply such an instruction to the address representing (decoding to) the receive FIFO and simultaneously to the transmit FIFO, the receive data would be read from the receive FIFO, modified by the instruction, and written to the transmit FIFO. In general, this is not likely the desired operation. However, this may be what is desired. So the RMW instruction applied to the the address of the receive/transmit FIFOs transforms the receive data and transmits the modified data in a single instruction cycle.

The Intel architectures support a separate address space for I/O devices. The claim is that the situation described above can't occur in a microprocessor with separate I/O and memory spaces. In most cases that is true, but as you can imagine, being able to apply a data transformation in a single cycle using memory-mapped I/O is very likely to be faster that the same transformation using IN and OUT instructions. On the other hand, not giving up memory address space to I/O devices may be just as important. Finally, there's no reason why an Intel microprocessor cannot use memory-mapped I/O.

Thus, if you'll contact Daryl by PM, you may be able to buy a pre-programmed decoder device from him, or he may point you to any open source files of programming for the device.

(Edit: corrected some grammatical errors as pointed out by Garth.)

In this case, how does 8080 I/O address decoding work. I can connect and 8224 and an 8228, and only have one I/O chip

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Mon Nov 04, 2013 12:56 pm
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James_Parsons:

Addresses are just references to some resource. In most cases, addresses from any computer refer to a location in the memory of the computer. However, there's nothing particularly significant about an address being in the memory of the computer. There exists a concept of an address space that is used in programming and computer architectures. In programming, the concept is used to allow the segregation of various functions, subroutines, variables, etc. into common and/or separate spaces where the names of the objects can be the same as those in the other spaces. The space allows the tools (compilers, assemblers, and linkers in programming), and address decoders (computer architectures) to separate these objects from others having the same names.

Memory-mapped I/O shares the same name space as regular data or program objects. I/O-mapped I/O is in a separate and distinct name space. The decoders for these name spaces must have some indication from the processor that the address is in one space or the other. Thus, processors like the Data General Nova, the Intel 8080/8085/8086/80186/80286/80386/80486... and the Z80/Z180/Z8000/Z8001/Z8002/... use special instructions for accessing the I/O name space, and the remaining instructions to access the memory name space.

The Data General Nova used dedicated instructions for accessing I/O devices. I/O devices in the Data General architecture were expected to be composed of a small number of output registers and input registers. The I/O instructions of the Data General Nova allowed these distinct registers to be accessed by encoding the addresses of the registers and the operations to be performed directly in the I/O instructions. An indirect operation, where the address of one of the I/O registers was held in a processor register, was not allowed for the I/O name space.

The Intel and Zilog processors generally use only two special instructions, IN and OUT, to access the I/O name space. When those instructions are encountered by the instruction decoder, the processor asserts the IO control signal. When this signal is asserted, the memory name space is disabled and all decoders for that name space are not active. On the other hand, the I/O name space decoders are enabled. This allows the "same" address on the processor's address bus to select one object and not the other even though the "addresses" are the same.

These processors also use the concept of direct and indirect addresses for the IN and OUT instructions. With direct (8-bit direct zero page or the 16-bit direct absolute addressing modes of the 6502), the instruction contains the address. With the indirect mode, equivalent to the 6502 indirect zero page addressing mode, a processor register contains the address of the I/O name space location that should be accessed. In either of these cases, the address pins of the processor provides the value that must be resolved to select to desired object.

The MOS6502 and Motorola MC6800 do not have a separate name space for memory and I/O. Thus, a decoder for these processors need only consider the address provided by the processor. On the 8080/Z80, in addition to the address provided by the processor, the IO/nM signal must be included in the decoding logic so that the two name spaces can be separated. In the 8080, only 256 I/O space addresses are provided, so the decoding is simpler than in the 8086/Z8002 which provide a 16-bit I/O space.

Note that since the 8080/Z80 provide the IO/nM signal as a control signal during each and every valid memory or I/O access cycle, it is possible to place I/O devices in the I/O space or in the memory space. The only real difference between an address decode for I/O devices in memory space or I/O devices in the I/O space is the use of the IO/nM signal as an additional qualifer for decoder. Simply restricting the processor address to a particular page (256 bytes) of memory, the 8080/Z80 I/O can easily implement memory-mapped I/O.

Hope this helps you understand the difference between the memory-mapped and I/O-mapped name spaces.

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Mon Nov 04, 2013 11:39 pm
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How do i read a specific pin. For example how do i read pb1 on a pia

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Thu Nov 07, 2013 3:56 pm
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Quote:
How do i read a specific pin, for example how do i read PB1 on a PIA?

Read PB, and to single out bit 1, you can AND it with 00000010B which has a 1 in bit 1's place. Depending on the instruction set, there may be other ways to do it, like with the 65c02's BIT instruction or, in the rare situation that I/O is in ZP (as it was in some microcontrollers), its BBS and BBR instructions, which specified, all in one two-byte instruction, the address to look at, the bit number within that byte to test, the branch condition, and the branch distance. The BIT instruction normally uses a mask in the accumulator telling which bits to test (resulting in the Z flag status); but if you want to test bit 6 or bit 7, you don't need the mask because they are automatically loaded into the V and N status flags whose condition (set or clear) you can then branch on by using BVC, BVS, BPL, or BMI.

For changing individual output bits, the most obvious way is to load the port byte into the accumulator, AND-out or OR-in (or XOR to toggle) the desired bit(s), and store the modified byte back to the port. On the 65c02 you can also use the TSB and TRB instructions which again use a mask in the accumulator to test and set or reset bits, or, in the again-rare situation that you have I/O in ZP, the SMB or RMB instructions. If you want to toggle bit 0 of a port with a single instruction and you already know its value, you can use INC (to make the port go from xxxxxxx0 to xxxxxxx1) or DEC (to make the port go from xxxxxxx1 to xxxxxxx0). These and other tips are on the program tips page in my 6502 primer, at http://wilsonminesco.com/6502primer/PgmTips.html . You'll see that the instruction set may affect what I/O bits you choose to put various things on, since good choices can allow you to make your code more efficient.

As a caveat, there's a situation where the above instructions by themselves might not be the best, and that is if you have open-drain bits on the port with an external pull-up resistor. (The benefit of this kind of output is that it can be pulled down by any of two or more sources, as is the case with the popular I2C synchronous-serial interface.) If the IC should not be pulling a bit down at the moment, but something external is pulling the line down, what can happen if the IC reads the pin instead of the output register is that you would read a 0 and store it back that way as one of the supposedly unchanged bits, so now the port really is pulling that bit down when it should not. The solution for that is to also keep a record in a RAM variable telling what it should be.

I have code posted for bit-banging I2C (more correctly written I²C) at http://wilsonminesco.com/6502primer/GENRLI2C.ASM showing the use of these various instructions and also writing to the 6522's data-direction register for effectively getting an open-drain configuration on an IC that wasn't really made for it.

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Thu Nov 07, 2013 7:14 pm
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In that case, how do I read PB

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Fri Nov 08, 2013 12:56 pm
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LDA VIA_PB (or some variation on that). If you're using the 6520/6820 PIA, it might be LDA PIA_PB, or LDAA PIA_PB, or similar. Somewhere near the top of your code you should have the addresses of the I/O registers like what I have about a third of the way down the page at http://wilsonminesco.com/6502primer/PgmWrite.html . That way you can use the name of the register instead of having to remember the address; and if the address does change, you can change it in one place and the assembler will carry the change through to every place that refereces the register by name.

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Fri Nov 08, 2013 8:44 pm
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I need help learning I/O decoding for an 8080. There doesnt semm to be a lot of hardware documentation on this cpu First off, if it has a seperate space for I/O does that mean that i can do 32k RAM, 32k ROM, and then worry about I/O. Then how is I/O decoding different than memory address decoding. If possible can i see a simple example

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Mon Nov 11, 2013 3:58 pm
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Quote:
does that mean that i can do 32k RAM, 32k ROM, and then worry about I/O
Hi, James. Yes, that's right.

6500 and 6800 series cpu's (and some others) have no special instructions to deal with Input/Output operations. Luckily, it's not difficult for a cpu to treat I/O devices as memory. The same instructions used for memory (eg: LDA and STA) can also be used for I/O. But it is necessary for the decode circuitry to set aside a small portion of the memory map for use by the I/O device. That means the total amount of memory will be somewhat less than 64K.

8080, 8085, Z80 and 8086 (x86) series cpu's (and others) offer a different approach. There's nothing to prevent them from using memory mapped I/O -- it is still possible. However, most people take advantage of IN and OUT instructions provided with these cpu's. These behave similarly to LDA and STA -- there is a transfer to/from the cpu, according to an address provided by the cpu. But the decode circuit is simpler, for two reasons:

  • depending on the cpu, the address may only be 8 bits (not 16)
  • the cpu has extra control signal outputs. As well as a set for memory operations (perhaps called /RD and /WR ), there's also a set for I/O operations (maybe called /IORD and /IOWR ). These activate in response to IN and OUT instructions.

If you want to study circuit examples, I suggest you search for Z80, not 8080. There are many good reasons why the 8080, while historically important, is no longer used. One reason is the complexity of its control signal outputs -- it is typically necessary to include a 8228 or 8238 system controller IC. (Also, the 8080 needs three separate power supplies!)

-- Jeff

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Last edited by Dr Jefyll on Mon Nov 11, 2013 10:50 pm, edited 1 time in total.



Mon Nov 11, 2013 10:26 pm
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(Edit: corrected the term "memory mapped IO" to "non memory-mapped IO" per Dr Jefyll, Thanks for the pointer. Also noted an error in the 8080 example decoder. the 8080/8228 signals nIOR and nIOW are already active low and do not need to be inverted as shown in the first diagram. Added a second diagram, with the correction made. In the second diagram, the 8080/8228 signals nIOR and nIOW are connected directly to the nE pin of the 74xx139 decoder.)

James_Parsons:

I guess I didn't make it clear enough for you in my previous reply.

When a processor supports various different kinds of memory, i.e. program memory, data memory, stack memory, and I/O, it must also provide the means by which to detect these differences and allow external decoders to multiplex (read) and demultiplex (write) the various memory and I/O devices.

For the 8080, the processor provides a status pin(s) that define whether the transaction on the bus is a memory read, memory write, I/O read, or I/O write. There are several bus cycle status pins that the 8080 microprocessor provides that you must decode separately to define the various operations and spaces for the bus transaction.

I referred you to bitsavers.org in an earlier post for the MCS-4 datasheets. If you'll go to that directory and go up one level, you'll find full datasheets and user's manual for the 8080 and 8085 microprocessors. In addition, you'll find the programmer's reference manuals for these two 8-bit predecessors to the 8086/8088 microprocessors.

In Intel's vernacular, the 4004 microprocessor family was known as the MCS-4/MCS-40. Similarly, the Intel vernacular for the 8080/8085 was MCS-80/85. MCS stands for Micro Computer System.

If you use the 8080, then you are also likely to be using the 8224 Clock Generator and Driver and the 8228 System Controller. The 8085 microprocessor's biggest advantage over its predecessor is that it incorporated the functions of the 8224 and the 8228, which greatly simplified the task of interfacing program/data memory and I/O devices to this family.

The 8228 provides four cycle control signals that you can use for decoding: nMEMR, nMEMW, nIOR, and nIOW. The 8085 provides similar signals: IOnM, nRD, and nWR.

When attaching to an 8085, simply connect IOnM and some of the 8 address lines that represent the IO port address, to a decoder. If using a 74xx139, an inverter (74xx04, 74xx14, or 74xx00) is used to invert the IOnM signal. The inverted signal is tied to the active low nE control line of the 74xx139. Attach address lines A0 and A1 to the 74xx139 A and B inputs. This configuration provides 4 decoded output (repeated every four addresses).

I've attached a diagram representing the same decoder for the 8085 and then 8080/8228 (I incorrectly labeled the 8080 example as being the 8080/8224 rather than the 8080/8228. (Since I didn't save the schematic, you'll have to make the adjustment.)

Hope the figure helps you understand the non memory-mapped IO concept as exemplified by the 8080/8085 and Z80 microprocessors. The key being that the processor or some controller, i.e. 8228, provides dedicated signals that signify the type of memory cycle to any decode logic.

Attachment:
File comment: 8085 and 8080/8228 IO Decode Example
8080_DecoderExample.JPG
8080_DecoderExample.JPG [ 181.18 KiB | Viewed 5736 times ]

Attachment:
File comment: Corrected 8080 IO Decode Example
IO-Decode-8080.JPG
IO-Decode-8080.JPG [ 172.1 KiB | Viewed 5720 times ]

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Last edited by MichaelM on Tue Nov 12, 2013 2:38 pm, edited 1 time in total.



Mon Nov 11, 2013 10:49 pm
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Garth wrote:
LDA VIA_PB (or some variation on that). If you're using the 6520/6820 PIA, it might be LDA PIA_PB, or LDAA PIA_PB, or similar. Somewhere near the top of your code you should have the addresses of the I/O registers like what I have about a third of the way down the page at http://wilsonminesco.com/6502primer/PgmWrite.html . That way you can use the name of the register instead of having to remember the address; and if the address does change, you can change it in one place and the assembler will carry the change through to every place that refereces the register by name.

Is there a certain amount of memory I have to give to the PIA. Once I have that, how will I know what the PB data PA data and status register locations are

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